ON SPORTS Search Results

Contextual Info: DIGITAL SPORTS & THE NEW MILLENIUM: Opportunities from Online to On-Air Tom Galvin Director, Content Group Intel Corporation October 14, 1998 ² “The greatest contribution we can make is to use television and make it so you can see sports better on television

Contextual Info: HYFIRE VII Series Electronic Ignition Controls Instruction Manual Part#: 667S FORM 1468 REV. B 9/00 INSTALLATION INSTRUCTIONS ® HYFIRE® VIIS SPORTSMAN CD IGNITION SYSTEM Part No. 667S 4–12 Cylinder Notice: This product is legal for sale or use only on vehicles which may never be used on highways.

Contextual Info: FORM 1468 REV. B 9/00 INSTALLATION INSTRUCTIONS HYFIRE® VIIS SPORTSMAN CD IGNITION SYSTEM Part No. 667S 4–12 Cylinder Notice: This product is legal for sale or use only on vehicles which may never be used on highways. The HYFIRE® VIIS Sportsman CD Ignition Controls are not compatible with distributorless systems or

ADSP2116x

Contextual Info: a SHARC Processor ADSP-21365 SUMMARY Single-instruction, multiple-data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

ADSP-2100

Abstract: ADSP-21ESP202 D1851 ESP202
Contextual Info: a Mixed Signal/Embedded Speech Processor Preliminary Technical Data ADSP-21ESP202 PERFORMANCE FEATURES • 40K Bytes of On-Chip RAM, Configured as 8K Words On-Chip Program Memory RAM and 8K Words On-Chip Data Memory RAM • 20.3 ns instruction Cycle Time @ 3.3 Volts,

STR - Z 2062

Abstract: ADSP-2101
Contextual Info: ANALOG ► DEVICES FEATURES Complete DSP Microcomputer 60 ns Instruction Cycle Time from 16.67 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Word of On-Chip Data Memory RAM Separate Program and Data Buses On-Chip

smd w04 77

Abstract: smd B07 P03
Contextual Info: a SHARC Processor ADSP-21367 Preliminary Technical Data SUMMARY Single-instruction multiple-data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

Contextual Info: BACK ADSST – MPEG – 15XX Analog Devices can supply a software library which performs real time MPEG1 audio encoding for layer 1 and 2 on the ADSP2185. Please contact Kudos for full information on this package. The full ADSP2185 data sheet starts on the next

Contextual Info: a SHARC Processor ADSP-21367 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

PQFP-128 footprint

Abstract: EMS A100 circuit CL 2181 ADSP-2181
Contextual Info: BACK ADSST – MPEG – 10XX Analog Devices can supply a software library which performs real time MPEG1 audio encoding for layer 1 and 2 on the ADSP2181. Please contact Kudos for full information on this package. The full ADSP2181 data sheet starts on the next

ADSP-21367

Abstract: ADSP-21368 CP-1201
Contextual Info: a SHARC Processor ADSP-21368 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

three phase inverters circuit diagram

Contextual Info: a SHARC Processor ADSP-21367 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

Contextual Info: SHARC Processor SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational architecture On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip

dts master audio DL 1200

Abstract: ADSP-21365 CP-1201 Dolby prologic IIx decoder
Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

dts master audio DL 1200

Abstract: 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP21365 ADSP-21365 CP-1201
Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

ADSP21992

Abstract: ADSP-21992
Contextual Info: a Mixed Signal DSP Controller With CAN ADSP-21992 KEY FEATURES ADSP-219x, 16-Bit, Fixed Point DSP Core with up to 160 MIPS Sustained Performance 48K Words of On-Chip RAM, Configured as 32K Words On-Chip 24-Bit Program RAM and 16K Words On-Chip 16-Bit Data RAM

ADSP-21990

Contextual Info: a Mixed-Signal DSP Controller ADSP-21990 FEATURES ADSP-2199x, 16-bit, fixed-point DSP core with up to 160 MIPS sustained performance 8K words of on-chip RAM, configured as 4K words on-chip, 24-bit program RAM and 4K words on-chip, 16-bit data RAM External memory interface

AD183x

Contextual Info: a SHARC Processor ADSP-21363 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21363 is available with a 333 MHz core instruction

ADSP-21363

Abstract: ADSP-21160 ADSP-21161 ADSP21363 pcb thermal Design guide trace theta layout
Contextual Info: a SHARC Processor ADSP-21363 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21363 is available with a 333 MHz core instruction

usb modem e153

Abstract: IBM POWER3 processor 40A00000 E20A package Foot Pattern 41L6173 E212 mca date sheet of btu 25C38 20EE0007 e174
Contextual Info: RS/6000 44P Series Model 170 Service Guide SA38-0560-01 Second Edition October 2000 Before using this information and the product it supports, read the information in “Safety Notices” on page xi, “Appendix A. Environmental Notices” on page 267, and “Appendix B. Notices” on page 269.

SA38-0580-00

Abstract: SA38-0538 IBM POWER3 processor 7852-400
Contextual Info: p Series 640 Model B80 User’s Guide SA38-0580-00 First Edition October 2000 Before using this information and the product it supports, read the information in “Safety Notices” on page ix, “Appendix A. Environmental Notices” on page 153, and “Appendix B. Notices” on page 155.

ADSP-21160

Abstract: ADSP-21161 ADSP-21364 CP-1201 ADSP-21364SBSQZENG tbdm
Contextual Info: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction

AD150

Contextual Info: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction