OUTPUTS14 Search Results

Contextual Info: HIGH-SPEED 36K 4K x 9-BIT SYNCHRONOUS DUAL-PORT RAM PRELIMINARY IDT70914S Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed clock-to-data output times — Military: 20/25ns (max.) — Commercial: 15/20/25ns (max.) • Low-power operation

ALL LAPTOP MOTHERBOARD CIRCUIT DIAGRAM

Abstract: icd2023 marking t9d CY2295PVL laptop motherboard block diagram laptop motherboard resistors CY2291 CY2292 CY2295 ICD2028
Contextual Info: -:îW jr CY2291 CY2292 CY2295 I 1 illlD D p y n n I?Q c Three-PLL General Purpose Clock Generator Features Configuration includes permanent shutdown options for unused PLLs and configurable clocks Suspend feature allows shutting down a factory con­ figurable set of PLLs and outputs with the S2 pin

555 7490 7447 7 segment LED display

Abstract: SN76670 SNF10 rsn 3404 rsn 3305 NPN TRANSISTORS LIST ACCORDING TO CURRENT, VOLTAG mc2051 SN76131 SN76005 Ross Hill SCR Contactor
Contextual Info: G ENERAL IN FO R M A TIO N INDEXES Numerical • Functional • Cross-Reference DISCRETE SEMICONDUCTORS A N D COMPONENTS O R D ER IN G INSTRUCTIO NS A N D M EC HA NICA L D ATA MACH IV PROCUREMENT SPECIFICATION L IN EA R CIRCUITS ECL CIRCUITS SERIES 54S/74S CIRCUITS

Contextual Info: BURR - BROW N DAC7528 ¡b b I CMOS Dual 8-Bit Buffered Multiplying DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • DOUBLE BUFFERED DATA LATCHES • SINGLE 5V SUPPLY OPERATION • ±1/2 LSB LINEARITY The DAC7528 contains two, 8-bit multiplying digitalto-analog converters DACs . Separate on-chip latches

Contextual Info: PRELIMINARY IDT709149S HIGH-SPEED 36K 4K x 9-BIT SYNCHRONOUS PIPELINED DUAL-PORT SRAM F e a tu re s ♦ 13ns cycle time, 76MHz operation in pipeline mode * Architecture based on Dual-Port SRAM cells - - Allow s fu ll sim ultaneous access from both ports

ALL LAPTOP MOTHERBOARD CIRCUIT DIAGRAM

Abstract: SP 8666 B LAPTOP CIRCUIT DIAGRAM MOTHERBOARD
Contextual Info: fax id: 3511 CY2291 / CY22911 CY2292 / CY2292I CY2295 / CY2295I Three-PLL General Purpose Factory EPROM Programmable Clock Generator • Phase-locked loop oscillator input derived from exter­ nal crystal 10 MHz to 25 MHz or external reference clock (1 MHz to 30 MHz)

MO-067-AC

Abstract: TIP 61 pin
Contextual Info: IDT70914S HIGH SPEED 36K 4K X 9 SYNCHRONOUS DUAL-PORT RAM Features * * High-speed clock-to-data output times - F ast 12ns clock to data out - M ilitary: 20125ns (max.) - S elf-tim ed write allow s fast cycle tim es - C o m m e rc ia l^ 2 /1 5/20ns (max.)

Contextual Info: CMX7861 FirmCODEC CML Microcircuits COMMUNICATION SEMICONDUCTORS DATASHEET D/7861_FI-1.x/2 June 2012 Advance Information 7861FI-1.x Programmable Baseband Interface Features Features Cont. •     o o o o o  o o  o o  o o  o  o

Contextual Info: IDT70914S HIGH SPEED 36K 4K X 9 SYNCHRONOUS DUAL-PORT RAM Features * * High-speed clock-to-data output times - F ast 12ns clock to data out - M ilitary: 20125ns (max.) - S elf-tim ed write allow s fast cycle tim es - C o m m e rc ia l^ 2 /1 5/20ns (max.)

ALL LAPTOP MOTHERBOARD CIRCUIT DIAGRAM

Abstract: LAPTOP CIRCUIT DIAGRAM MOTHERBOARD
Contextual Info: CY2291 CY2292 CY2295 CYPRESS Three-PLL General Purpose Clock Generator Configuration includes permanent shutdown options for unused PLLs and configurable clocks Suspend feature allows shutting down a factory con­ figurable set of PLLs and outputs with the S2 pin

tms 2300

Abstract: HIC037 transistor bf 175
Contextual Info: TMS4020NC • Mechanical data and pin alignments Add the following data: The TM S 40 20 NC is also available in a 22 pin dual-in line package w ith 400-m il spacing between leads. The pin assignments are as shown. FUNCTION PIN NO. FUNCTIC 1 2 3 4 5 6 Ag Ag

CMX7861

Abstract: CMX7861Q1 SDR baseband modulation demodulation
Contextual Info: CMX7861 CML Microcircuits FirmCODEC COMMUNICATION SEMICONDUCTORS D/7861_FI-1.x/1 December 2011 DATASHEET Advance Information 7861FI-1.x Programmable Baseband Interface Features Dual Channel Codecs o Can operate in modem or codec mode o Two ADCs 16 bit o Two DACs 14 bit