P08T Search Results

Contextual Info: P08TR0M C INDUSTMES BQJEVES THE DATA ON TH6 DRAWNG TO BE RELIABLE, SM CE THE TECHNCAL INFORMATION IS OMEN FREE OF CHARGE, THE USER EMPLOYS SUCH M FORMATION AT H S OWN OSCRETION ANO RISK. POSIfROMC MDU5TRES ASSUMES NO RESPO NSBUIY FOR RESULTS OBTAINED OR DAMAGES

Contextual Info: IM S OMMNG CONTAMS MFORMMION PROPRCTART TO POSITRONS R4D. MC. ANT REPRODUCTION, DISCLOSURE OR USE OF THIS DRNMNG B EXPRESSLY PROIP TCD. EXCEPT AS P08TR0MC IND. INC. MAY OTHERWISE AGREE M WRTTMO. DATE rev -9 OS NC REVISION RECORD EC O 24 2 77 APP DR (X YK

Contextual Info: P08TR0M C INDUSTMES BELCVES THE DATA ON TH 6 DRAWNG TO B E RELIABLE, SM C E THE TECHNICAL INFORMATION IS GNEN FREE O F CHARGE, THE USER EMPLOYS SUCH WFORMATION AT H 6 OWN D6CRETION AND RISK. POSTTRONIC M DÜSTRES ASSUM ES NO RESPO N SB U IY FOR RESULTS OBTAINED OR DAMAGES

Contextual Info: 2.50, :1 7 2.50 5.50 PART NO. Contacts MCs004-P02T MCs004-P03T MCs004-P04T MCs004-P05T MCs004-P06T MCs004-P07T MCs004-P08T MCs004-P09T MCs004-P10T MCs004-P11T MCs004-P12T MCs004-P13T MCs004-P14T MCs004-P15T 1X2 1X3 1X4 1X5 1X6 1X7 1X8 1X9 1X10 1X11 1X12 1X13

Contextual Info: SK3951 RECOUD P08TR0M C M OUSTRES BELCVES THE DATA ON TH 6 DRAWMG TO BE RELIABLE, SM CE THE TECHNICAL INFORMATION B GIVEN FREE OF CHARGE, THE USER EMPL0VS SUCH MFORMATION AT H 6 OWN DISCRETION AND RISK. POSmtONIC M OUSTRES ASSUM ES NO RESPONSM UTY FOR RESULTS OBIMNED OR DAMAGES

27A6

Contextual Info: TMS28F210 1048576-BIT FLASH MEMORY I SMJS210B - DECEMBER 1892 - REVISED JUNE 1995 N PACKAGE TOP VIE W Pin Compatible With Existing 1-Megabit EPROMs All Inputs/Outputs TTL Compatible Vcc Tolerance ±10% Maximum Access/Minimum Cycle Time ’28F210-10 100 ns

sn74als662

Abstract: sn74als663 sn74als662a SN74ALS853 2114D
Contextual Info: SN54ALS652, SN54A LS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SDAS066E - DECEMBER 1983 - REVISED JANUARY 1995 Bus Transceivers/Registers Independent Registers and Enables for

Contextual Info: SN54LVT273, SN74LVT273 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR I SCBS130E - MAY 1992 - REVISED JULY 1995 State-of-the-Art Advanced BICMOS Technology ABT Design for 3.3-V Operation and Low-Static Power Dissipation Support Mixed-Mode Signal Operation (5-V

3Y20

Contextual Info: SN75186 QUADRUPLE DRIVER/RECEIVER WITH LOOPBACK D3389. FEBRUARY 1990 FN PACKAGE Meets Standards RS-232-C, EIA-232-D, and CCITT V.28 TOP VIEW Four Independent Drivers and Receivers CM O Ü z S I—JI—] L J L J , A 3 2 1 1 LB ] 5 N < Loopback Mode Functionally Self-Tests

75SSS

Contextual Info: SN54ALS573C, SN54AS573A, SN74ALS573C, SN74AS573A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS048D- DECEMBER 1989 - REVISED JANUARY 1996 • 3-State Buffer-Type Outputs Drive Bus Lines Directly • Bus-Structured Pinout • True Logic Outputs

Contextual Info: SN74LVC112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET _ SCAS28BA-JANUARY 1 9 9 3 - REVISED JULY 1995 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC544 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS I SCAS346A - MARCH 1994 - REVISED JULY 1995 DB, DW, OR PW PACKAGE TOP VIEW Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C LEB A[ 1 U [ 2 A1[ 3 A2 [ 4 A3[ 5 A4[ 6 A5 [ 7

ADVANCED COMMUNICATION DEVICES

Abstract: ACD80800 ACD80900 ACD82216 ACD82224 16N03 P03R
Contextual Info: Advanced Communication Devices Corp ADVANCE INFORMATION Data Sheet: ACD82224 ACD82224 24 Ports 10/100 Fast Ethernet Switch Last Update: September 19, 2000 Please check ACD’ s website for update information before starting a design Web site: http://www.acdcorp.com

I 8432

Abstract: Memory Stick pinouts 82C50A LG tv remote circuit diagram T-75-37-05 0944D 303AL
Contextual Info: HARRIS SEMICOND SECTOR IS BE § 43QE571 D 0 1 [ m 4 1 | 0944 D 8 2 C 5 0 A GB h a r r i s CM OS Asynchronous Communications Element Pinouts DOC 1 01 C 2 02 C 3 03 C 4 40 3 vcc 04 C 5 OS c 6 36 □ CTS 35 ] HR 06 i 7 07 C a 34 3 0UT1 33 3 DTR 32 3 RTS 31 ] 0UT2

Contextual Info: SN54ALS874B, SN74ALS874B, SN74ALS876A SN74AS874, SN74AS876 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS SDAS061C - APRIL 1982 - REVISED JANUARY 1995 SN54ALS874B. . . JT PACKAGE SN74ALS874B, SN74AS874 . . . DW OR NT PACKAGE TOP VIEW • 3-State Buffer-Type Outputs Drive Bus

Contextual Info: SN74ALS994 10-BIT D-TYPE TRANSPARENT READ-BACK LATCH 3DAS237A - OCTOBER 1984- REVISED JANUARY 1986 • • • • 3-State l/O-Type Read-Back Inputs Bus-Structured Pinout True Logic Outputs Package Options Include Plastic Small-Outline DW Packages and Standard

HC4060 crystal

Abstract: HC4060 c4060
Contextual Info: SN54HC4060, SN74HC4060 14-STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS SCLS161A - DECEMBER 1982 - REVISED JANUARY 1996 Allow Design of Either RC or Crystal Oscillator Circuits Package Options Include Plastic Small-Outllne D and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),

Contextual Info: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SC LS 189C - FEBRUARY 1993 - REVISED APRIL 1986 EPIC Enhanced-Performance Implanted CMOS 2-|i Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc. Ta = 25°C Typical V q h v (Output Voh Undershoot)

Contextual Info: SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS I SCAS299A - JANUARY 1993 - REVISED JULY 1995 DB, DW, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) Submicron Process • Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

s561a

Contextual Info: TMS44100, TMS441 OOP, TMS46100, TMS46100P 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMHS561A - MARCH 1995 - REVISED JUNE 1995 Organization . . . 4194304 x 1 Single 5 V Power Supply, for TM S44100/P ±10% Tolerance Single 3.3 V Power Supply, for TM S46100/P

SN74LVC240

Contextual Info: SN74LVC240 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS I SCAS293A - JANUARY 1993 - REVISED JULY 1995 DB, DW, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25<>C

TMS6264

Contextual Info: TMS626402 2097152-WORD BY 4-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS842A - FEBRUARY 1994 - REVISED JUNE 1995 • Organization . . . 2M x 4 x 2 Banks DGE PACKAGE TOP VIEW • 3.3-V Power Supply (±10% Tolerance) • Two Banks fo r On-Chip Interleaving

texas instruments 77261

Abstract: TEXAS 77261 N03J
Contextual Info: TMS626802 1048576-WORD BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS182A - FEBRUARY 1994 - REVISED JUNE 1995 Organization . . . 1M x 8 x 2 Banks 3.3-V Power Supply ±10% Tolerance Two Banks for On-Chip Interleaving (Gapless Accesses) High Bandwidth - Up to 100-MHz Data

Contextual Info: SN74LVC257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS SCAS2948 - JANUARY 1993 - REVISED JULY 1995 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) Submicron Process l • ESD Protection Exceeds 2000 V Per