P304 V Search Results

Mifare plus protocol

Abstract: mifare plus functional specification Mifare plus commands Mifare plus 14443-4 command ISO 14443-4 Mifare plus security level 7816-4 iso 7816-4 mifare plus card
Contextual Info: P304/P308/P310G002 family Smart eID Rev. 01 — 29 July 2008 Product short data sheet 1. General description 1.1 Smart eID family approach The Smart eID family members feature a modular set of devices with: • • • • 4 KB to 10 KB EEPROM Secured triple-DES coprocessor

Varistor V471U

Abstract: v471u v431u V271U V391U V201U v820u Varistor V201U panasonic varistor v471u V241U
Contextual Info: “ZNR” Transient/Surge Absorbers Type D Straight Leads Cut Type (Bulk Type) • Ratings and Characteristics ✽ Refer to bulk standard type part no. (P304-P318). ■ Dimensions in mm (not to scale) T✽✽ φd B H D L✽ W notes ✽ Dimension “L”: Conforms to each individual specification.

Contextual Info: POWER DIVIDERS, 3 WAY- 0° AMPLITUDE PHASE FREQUENCY INSERTION 1 RANGE ISOLATION BALANCE BALANCE VSWR POWER RATING LOSS (dB) MAX (deg) MAX MAX (WATTS) (MHZ) (dB) MAX (dB) MIN 2.0 1-200 0.2 130 1 1 0.5 25 03 3.0 1-500 20 130 1 1.2 1 03 3.0 130 1 5-500 23

Contextual Info: POWER DIVIDERS, 3 WAY - 0° Frequency Range MHz Insertion Loss (dB) max. 0.5 1.2 1.0 1.2 1.5 1.0 0.8 1.5 1.5 1-200 1-500 5-500 10-1000 20-1000 100-1000 800-1000 50-1500 800-1500 Isolation (dB) min. Amplitude Balance (dB) max. Phase Balance (Deg) max. 25

P304

Contextual Info: POWER DIVIDERS, 3 WAY - 0° Frequency Range (MHz 1-200 1-500 5-500 10-1000 20-1000 100-1000 800-1000 50-1500 800-1500 Insertion Loss (dB) max. 0.5 1.2 1.0 1,2 1.2 1.0 0.8 1.5 1.5 Isolation (dB) min. Amplitude Balance (dB) max. Phase Balance (Deg) max. 25

192P sprague

Abstract: P347 Vishay Sprague 192P RF 3886 P 8712 sprague date code 192P104 sprague 192p
Contextual Info: Type 192P Pacer' Vishay Sprague P olyester Film /Foil C apacitors Sleeved, M iniature, A xial Lead FEATURES • Axial lead, designed for automatic insertion • Non-inductively wound, extended foil construction • Lead wire has metal end cap for connection to extended foil

192P sprague

Abstract: 192P102X9200 192P222X9200 sprague 192p 192P183 192P224X9200 192P104X9200 marking 192P 192P272X9080 192P332X9080
Contextual Info: Type 192P Pacer Vishay Sprague Polyester Film/Foil Capacitors Sleeved, Miniature, Axial Lead FEATURES • Axial lead, designed for automatic insertion • Non-inductively wound, extended foil construction • Lead wire has metal end cap for connection to extended

P239

Abstract: P181 P185 P-239 P212 P213 p178 P215 P216 P218
Contextual Info: XC4025 and XC4025E Pinout Table Pin Name VCC I/O A8 I/O(A9) I/O I/O I/O I/O I/O(A10) I/O(A11) I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O(A12) I/O(A13) I/O I/O I/O I/O I/O I/O I/O(A14) SGCK1(A15;I/O) VCC GND PGCK1(A16;I/O) I/O(A17)

P347

Abstract: 192P104
Contextual Info: fV -& 5 -0 -0 5 ' A COMPANY TYPE 192P PACER Polyester Film/Foil Capacitors Sleeved, Miniature, Axial Lead OF SPRAGUE FEATURES • Axial lead, designed for automatic insertion • Non-inductively wound, extended foil construction • Lead wire has metal end cap for connection to extended foil

J29 P190

Abstract: p331 TRANSISTOR p477 p525 P364 P521 G P440 C 05 P521 G2 p372 transistor P519
Contextual Info: MSX Family Data Sheet Features • SRAM-based, in-system programmable • Configurable I/O Ports – Individually programmable as input, output, bi-directional, or Bus Repeater mode – Control Signals per I/O port: 2 input enables, 2 output enables, 2 Global Clock inputs and Next Neighbor

transistor P239

Abstract: R33PI transistor 4287 AB P239 9 318 TI P272 w29 transistor P069 P04368 p055 IQB96
Contextual Info: The FPID Family Data Sheet Features Description Device I-Cube's family of FPID devices is available in a variety of I /O densities, ranging from 96 to 320 usable ports. The part number reflects the number of usable I/O s in the device. This family, from the

n4 p69

Abstract: v1 j p304 MQ240 P212 P213 P214 P215 PG223 XC4025 XC4025E
Contextual Info: Xilinx Common Package Footprints BG225 225-Pin Ball Grid Array XC4010BG225 (Bottom View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VCC PGCK2 (I/O) I/O I/O I/O I/O I/O VCC I/O N.C. I/O I/O I/O I/O VCC P SGCK2 (I/O) M0 I/O (HDC) I/O (LDC) N.C. I/O N.C. I/O (/INIT)

A2L6

Abstract: A3L12 a2l1 A3L10 CCD595 Contact image sensor fairchild P115 FAIRCHILD A3R16 P210 fairchild A1R8
Contextual Info: PRELIMINARY DATA SHEET CCD595 9216 x 9216 Pixel Image Area Full Frame CCD Image Sensor FEATURES • 9216 x 9216 Full Frame CCD Array • 8.75 µm x 8.75 µm Pixels • 80.64mm x 80.64mm Image Area • 100% Fill Factor • Non Multi-Pinned Phase MPP Operation

J29 P190

Abstract: L-29 p302 transistor p98 p115 p106 P191 transistor be p88 P142 P143
Contextual Info: XC4000XLA/XV Field Programmable Gate Arrays January 28, 1999 Version 1.0 0* R XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table

transistor D313 circuit diagram application

Abstract: c06-15 IC503 4013BT RC22H PHILIPS R114665 r 1206, r0603 philips resistor 2322 LDR 03 PHOTO RESISTOR Philips X7R
Contextual Info: APPLICATION NOTE Fiber optic transceiver board STM1/4/8, OC3,12,24, FC/GE AN98090 Philips Semiconductors Fiber optic transceiver board STM1/4/8, OC3,12,24, FC/GE Application Note AN98090 Abstract This application note describes demoboard OM5802. This demoboard is designed for customer demonstration of

J29 P190

Abstract: AG29 p115 p106 transistor be p88 XC4028XLA P142 P143 P144 P145
Contextual Info: XC4000XLA/XV Field Programmable Gate Arrays January 28, 1999 Version 1.0 0* R XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table

AB P89 zener

Abstract: Zener diode MARKING P035 252 B34 ZENER DIODE Zener diode MARKING P044 ZENER diode p317 Zener Diode p047 p014 DD 127 D TRANSISTOR zener AF4 on semiconductor marking code P008
Contextual Info: IQX Family Data Sheet FEATURES DESCRIPTION • SRAM-based, in-system programmable • Switch Matrix — Non-Blocking — Identical and predictable delays — One-to-one, one-to-many and many-to-one connections • RapidConfigure parallel interface for fast, incremental

P108t

Abstract: p055 TRANSISTOR P210 P106t p055 power transistor pb416 P089 ior p237 ior p135 P017H
Contextual Info: À I Cube IQ Fam ily Data Sheet Features Description • E ig h t d e v ic e s r a n g in g fro m 32 to 320 I / O P o rts • S R A M - b a s e d P r o g r a m m in g fo r In - s ys te m R e c o n f ig u r a b ilit y • S w it c h M a t r ix A r c h ite c t u r e

MARKING CODE p109

Abstract: 416L DD 127 D TRANSISTOR diode mark P019 IDS200 marking p020 p014 marking datasheet p022 P108 P183 kw
Contextual Info: IQX Family Data Sheet FEATURES DESCRIPTION • SRAM-based, in-system programmable • Switch Matrix — Non-Blocking — Identical and predictable delays — One-to-one, one-to-many and many-to-one connections • RapidConfigure parallel interface for fast, incremental

I-CUBE

Abstract: lp-032 IQX160-7PQ208 P124l P2G5 P1291
Contextual Info: i: * I- C u b IQX Family Data Sheet e m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQX family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using a 0.6|jm C M O S process. These devices offer clock speeds of up to 133 MHz and pin-to-pin delay as low

Contextual Info: Product Obsolete/Under Obsolescence R XC4000XLA Family Field Programmable Gate Arrays Package Pinouts XC4013XLA Pinout Table XC4013XLA Pinout Table Continued XC4013XLA Pinout Table PAD NAME PQ160 PQ208 PQ240 I/O – – P21 BG256 H1 PAD NAME PQ160 PQ208

MOSFET P239

Abstract: XC4000XLA VDR P275 L20 P55 MOSFET XC4000E XC4000X XC4000XL XC4000XV XC4013XLA XC4028XLA
Contextual Info: XC4000XLA/XV Field Programmable Gate Arrays R February 1, 1999 Version 1.0 6* Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC4000XLA devices are improved versions of XC4000XL devices. The XC4000XV devices have the

Contextual Info: "1 T l-C u b e IQX Family Data Sheet Features Description • SRAM-based, in-system programmable • Switch Matrix - Non-Blocking - Identical and predictable delays - One-to-one, one-to-many and many-toone connections • I/O Ports - Individually programmable as

Contextual Info: 1-Cube IQ Family Data Sheet Description Features • E ight d evices ra n g in g from 32 to 320 I / O P orts • SR A M -based P ro g ra m m in g for In-system R econfigurability • Sw itch M atrix A rchitecture • N on-blocking • P redictable & U niform D elays