LCC-48P-M03
Abstract: No abstract text available
Text: C-LEADED SMALL OUTLINE PACKAGE FUJITSU SEMICONDUCTOR DATA SHEET 48 PIN PLASTIC LCC-48P-M03 48-pin plastic CSOP Lead pitch 0.40 mm Package width x package length 10.0 × 9.50 mm Sealing method Plastic mold Mounting hight 1.0 mm MAX LCC-48P-M03 48-pin plastic CSOP
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LCC-48P-M03
48-pin
LCC-48P-M03)
C48056S-1C-1
LCC-48P-M03
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Untitled
Abstract: No abstract text available
Text: BUMP CHIP CARRIER FUJITSU SEMICONDUCTOR DATA SHEET 48 PIN PLASTIC LCC-48P-M02 48-pin plastic BCC Lead pitch 0.50 mm Package width x package length 7.00 mm × 7.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX LCC-48P-M02 48-pin plastic BCC
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LCC-48P-M02
48-pin
LCC-48P-M02)
C48055S-c-4-2
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9806
Abstract: Package 48 LCC
Text: BUMP CHIP CARRIER FUJITSU SEMICONDUCTOR DATA SHEET 48 PAD PLASTIC LCC-48P-M02 Lead pitch Vertical: 0.5 mm Horizontal: 0.5 mm Package width x package length 7.0 × 7.0 mm Sealing method Plastic mold 48-pads plastic BCC LCC-48P-M02 48-pads plastic BCC (LCC-48P-M02)
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LCC-48P-M02
48-pads
LCC-48P-M02)
C48055SC-1-1
9806
Package 48 LCC
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QFN048-C-S560-1
Abstract: LCC-48C-A01
Text: LEADLESS CHIP CARRIER FUJITSU SEMICONDUCTOR DATA SHEET 48 PAD CERAMIC LCC-48C-A01 EIAJ code :∗QFN048-C-S560-1 48-pad ceramic LCC Lead pitch 40 mil Package width x package length 560 × 560 mil Sealing method Metal seal LCC-48C-A01 48-pad ceramic LCC (LCC-48C-A01)
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LCC-48C-A01
QFN048-C-S560-1
48-pad
LCC-48C-A01)
C4800(
C48001SC-4-2
QFN048-C-S560-1
LCC-48C-A01
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LCC-48C-A01
Abstract: CERAMIC LEADLESS CHIP CARRIER PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC QFN048-C-S560-1
Text: LEADLESS CHIP CARRIER FUJITSU SEMICONDUCTOR DATA SHEET 48 PAD CERAMIC To Top / Package Lineup / Package Index LCC-48C-A01 EIAJ code :∗QFN048-C-S560-1 48-pad ceramic LCC Lead pitch 40 mil Package width x package length 560 × 560 mil Sealing method Metal seal
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LCC-48C-A01
QFN048-C-S560-1
48-pad
LCC-48C-A01)
C48001SC-4-2
LCC-48C-A01
CERAMIC LEADLESS CHIP CARRIER
PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC
QFN048-C-S560-1
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Package 48 LCC
Abstract: QFN048-C-S560-1 LCC 48 CERAMIC LEADLESS CHIP CARRIER LCC-48C-A01 PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC 40MIL
Text: LEADLESS CHIP CARRIER 48 PAD CERAMIC LCC-48C-A01 EIAJ code : ∗QFN048-C-S560-1 Lead pitch 40mil Package width x package length 560 × 560mil Sealing method Metal seal 48-pad ceramic LCC LCC-48C-A01 *Shape of PIN NO.1 INDEX : Subject to change without notice.
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LCC-48C-A01
QFN048-C-S560-1
40mil
560mil
48-pad
LCC-48C-A01)
C48001SC-4-2
Package 48 LCC
QFN048-C-S560-1
LCC 48
CERAMIC LEADLESS CHIP CARRIER
LCC-48C-A01
PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC
40MIL
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Untitled
Abstract: No abstract text available
Text: 48 MHz SAW Filter 3.5 MHz Bandwidth Part Number SF0048BA02645S DESCRIPTION • • • 48 MHz SAW bandpass filter with 3.5 MHz bandwidth. 13.3 x 6.5 mm ceramic LCC package. RoHS compliant. . . 1 1 - TYPICAL PERFORMANCE . 2 1 - . 1 - . 3 1 - . 2 - . 4 1 - .
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SF0048BA02645S
DSSF0048BA02645S
BA02645S
10-Feb-11
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SF0048BA02644S
Abstract: DSSF0048BA02644S
Text: 48 MHz SAW Filter 10 MHz Bandwidth Part Number SF0048BA02644S DESCRIPTION • • • 48 MHz SAW bandpass filter with 10 MHz bandwidth. 10 x 6.5 mm ceramic LCC package. RoHS compliant. TYPICAL PERFORMANCE . 1 . 2 . 3 . 4 . 5 - dB . 6 . 7 . 8 . 9 . 1 . 1 1
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SF0048BA02644S
BA02644S
DSSF0048BA02644S
24-Aug-2009
SF0048BA02644S
DSSF0048BA02644S
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DSSF0048BA02645S
Abstract: No abstract text available
Text: 48 MHz SAW Filter 3.5 MHz Bandwidth Part Number SF0048BA02645S DESCRIPTION • • • 48 MHz SAW bandpass filter with 3.5 MHz bandwidth. 13.3 x 6.5 mm ceramic LCC package. RoHS compliant. TYPICAL PERFORMANCE . . 1 . 2 . 3 . 4 . 5 - dB . 6 . 7 . 8 . 9 z H
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SF0048BA02645S
BA02645S
DSSF0048BA02645S
24-Aug-2009
DSSF0048BA02645S
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SF1575BA02534S
Abstract: marking SB
Text: 1575.42 MHz SAW Filter 48 MHz Bandwidth Part Number SF1575BA02534S DESCRIPTION • • • 1575.42 MHz SAW bandpass filter with a 48 MHz bandwidth for GPS applications. 2 x 1.6 mm LCC package, 4 pads. RoHS compliant. TYPICAL PERFORMANCE Amp 10 dB/div Amp 1 dB/div
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SF1575BA02534S
DSSF1575BA02534S
3-Jan-11
SF1575BA02534S
marking SB
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Untitled
Abstract: No abstract text available
Text: 48 MHz SAW Filter 10 MHz Bandwidth Part Number SF0048BA02644S DESCRIPTION • • • 48 MHz SAW bandpass filter with 10 MHz bandwidth. 13.3 x 6.5 mm ceramic LCC package, 12 pads. RoHS compliant. TYPICAL PERFORMANCE . 1 . 2 . 3 . 4 . 5 . 6 - dB . 7 . 8 . 9
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SF0048BA02644S
DSSF0048BA02644S
10-Feb-11
BA02644S
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Untitled
Abstract: No abstract text available
Text: SLC-25-7-2-XXX Optical SONET OC-48/SDH STM-16 SFF LC 2x5 Transceiver - 2.488GBaud - +3.3V " PR EL IM IN AR Y Features ! 2.488 Gbps SONET/SDH OC-48 Compliant ! Compliant to Bellcore GR-253 and ITU-T G.957 specification. ! Die Cast Metal Package ! 100Ω differential AC coupled CML PECL Interoperable
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SLC-25-7-2-XXX
OC-48/SDH
STM-16
488GBaud
SLC-25-
SLC-25-7-2-XX
SLC-25-7-2-XXH
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68-JLCC package
Abstract: LUPA-1300 LUPA-300
Text: PRELIMINARY CYIL1SM0300AA-QBC LUPA-300 CMOS Image Sensor 80 MHz pixel rate. It is housed in a 48-pin ceramic LCC package. The sensor is available in a Monochrome version or Bayer RGB patterned color filter array Applications • • Machine vision Motion tracking
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CYIL1SM0300AA-QBC
LUPA-300
48-pin
250fps
68-JLCC package
LUPA-1300
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Untitled
Abstract: No abstract text available
Text: a FEATURES 80 M Hz Pipelined Operation Triple 10-Bit D/ A Converters RS-343A/ RS-170 Compatible Outputs TTL Compatible Inputs +5 V CM OS M onolithic Construction 40-Pin DIP Package ADV7121 44-Pin PLCC Package (ADV7122) 48-Lead TQFP (ADV7122) CMOS 80 MHz, Triple 10-Bit Video DACs
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10-Bit
RS-343A/
RS-170
40-Pin
ADV7121)
44-Pin
ADV7122)
48-Lead
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Untitled
Abstract: No abstract text available
Text: Preliminary CMOS SRAM KM68FS2000Z, KM68FR2000Z Family Document Title 256Kx8 SUper Low Power and Low Voltage Full CMOS SRAM Data Sheets for 48-CSP Revision History Rev No. History Draft Data Remark Rev. 0.0 - 1 st edition - Package Dimension Finalized Feb. 6 th, 1997
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KM68FS2000Z,
KM68FR2000Z
256Kx8
48-CSP
55/Typ.
32/Typ.
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Untitled
Abstract: No abstract text available
Text: KM616V4010C, KM616U4010C Family CMOS SRAM 256Kx16 bit Low Power and Low Voltage CMOS Static RAM with 48-CSP Chip Scale Package Revision No. 0.0 0.01 0.1 1.0 Draft Date Remark I nitial draft - UB/LB power control Errata correction July 4, 1998 Preliminary
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KM616V4010C,
KM616U4010C
256Kx16
48-CSP
KM616V4010C
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Untitled
Abstract: No abstract text available
Text: Preliminary CMOS SRAM KM68FS1000Z, KM68FR1000Z Family Document Titie 128Kx8 Super Low Power and Low Voltage Full CMOS SRAM Data Sheets for 48-CSP Revision History Rev. No. History Draft Data Rem ark Rev. 0.0 - 1 st edition - Package Dimension Finalized Feb. 6 th, 1997
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KM68FS1000Z,
KM68FR1000Z
128Kx8
48-CSP
55/Typ.
32/Typ.
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Untitled
Abstract: No abstract text available
Text: HD7 4 LVC16240A 16-bit Buffers / Line Drivers with 3-state Outputs HITACHI Description The HD74LVC16240A has sixteen inverter drivers with three state outputs in a 48 pin package. This device is a inverting buffer and has two active low enables 1G to 4G . Each enable independently
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LVC16240A
16-bit
HD74LVC16240A
HD74LVC16240A
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Untitled
Abstract: No abstract text available
Text: Preliminary CMOS SRAM KM616FS1000Z, KM616FR1000Z Family Document Titie 64Kx16 SUper Low Power and Low Voltage Full CMOS SRAM Data Sheets for 48-CSP Revision History Rev. No. History Draft Data Rem ark Rev. 0.0 - 1 st edition - Package Dimension Finalized Feb. 4 th , 1 9 9 7
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KM616FS1000Z,
KM616FR1000Z
64Kx16
48-CSP
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Untitled
Abstract: No abstract text available
Text: HD74LVC16241 16-bit Buffers / Line Drivers with 3-state Outputs HITACHI Description The HD74LVC16241 has sixteen buffer drivers with three state outputs in a 48 pin package. This device is a non inverting buffer and has two active low enables 1G, 4G , high enables (2G, 3G). Each enable
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HD74LVC16241
16-bit
HD74LVC16241
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29F800TA
Abstract: 29f800ba MBM29F800 29F800T
Text: • FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP I (Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type)
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48-pin
44-pin
F9811
29F800TA
29f800ba
MBM29F800
29F800T
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Untitled
Abstract: No abstract text available
Text: HD74LVC16241-16-bit Buffers I Line Drivers with 3-state Outputs Description The HD74LVC16241 has sixteen buffer drivers with three state outputs in a 48 pin package. This device is a non inverting buffer and has two active low enables 1G, 4G , high enables (2G, 3G). Each enable
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HD74LVC16241-------16-bit
HD74LVC16241
HD74LVG16241
HD74LVC16241
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Untitled
Abstract: No abstract text available
Text: DISTINCTIVE CHARACTERISTICS • Single 3.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard word-wide pinouts 48-pin TSOP Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type
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48-pin
44-pin
F48030S-1C-1
0981MAX
Q25lMAX
F44023S-1C-2
374T75b
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Untitled
Abstract: No abstract text available
Text: HD7 4 LVC16244A 16-bit Buffers / Line Drivers with 3-state Outputs HITACHI Description The HD74LVC16244A has sixteen line drivers with three state outputs in a 48 pin package. This device is a non inverting buffer and has two active low enables 1G to 4G . Each enable independently controls
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LVC16244A
16-bit
HD74LVC16244A
HD74LVC16244A
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