PARER Search Results

radar detector detector 10-25 ghz

Abstract: A7- B14 Radar Warning Receiver 6 pin DCI DCI circuit diagram ADF4350 TCI-1-13M AD9129 AD9129-MIX-EBZ nsd 102
Contextual Info: Preliminary Technical Data FEATURES DAC Update Rate of up to 5.6 GSPS Direct RF Synthesis @ 2.8 GSPS Data Rate DC-to-1.4 GHz in Baseband Mode DC-to-1.0 GHz in 2x Interpolation Mode 1.4 to 4.2 GHz in Mix-Mode Bypassable 2x Interpolation Excellent Dynamic performance

Cx2829

Abstract: ,national semiconductor Linear brief lb-3
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

ARM926T

Abstract: ic str 6454 s11 stopping compound motorola 7824 BT OSC26M CNC DRIVES ptc temperature sensor 400c 4*4 matrix keypad 17521 rca SAMSUNG NAND FLASH K9F5608
Contextual Info: i.MX21 Applications Processor Reference Manual Document Number: MC9328MX21RM Rev. 3 04/2007 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370

TAG 8926

Abstract: Lpg 899 SDC 2921 TF 6221 HEN LED display 12V+RELAY+1+C/8 pin ic sdc 3733
Contextual Info: MCIMX31 and MCIMX31L Multimedia Applications Processors Reference Manual MCIMX31RM Rev. 1 2/2006 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130

S3019A

Abstract: EV3019 S3019 SJ300
Contextual Info: EV3019 EV3019 SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD SONET/SDH/ATM STS-12 TRANSCEIVER EVALUATION BOARD DESCRIPTION The S3019 evaluation board provides a flexible platform for verifying the operation of the S3019 transceiver interface circuit. This document provides information on the board contents. It should be used in conjunction with

1553B

Abstract: MARCONI
Contextual Info: MRTU 55000 MIL-STD- 1553B REMOTE TERMINAL BUS CONTROLLER PRELIMINARY DATA Marconi GENERAL DESCRIPTION Electronic Devices FEATURES PERFORMS THE COMPLETE DUAL REDUNDANT REMOTE TERMINAL AND BUS CONTROLLER PROTOCOL FUNCTIONS OF MIL-STD-1553B The MRTU 55000 is a complete dual redundant

PL084

Abstract: PL-084
Contextual Info: P relim inary Am7984A Advanced Micro Devices FDDI ENcoder DECoder ENDEC DISTINCTIVE CHARACTERISTICS • Implements 4B/5B encoding/decoding as specified by the ANSI X3T9.5 Fiber Distributed Data Interface (FDDI) standard a Elasticity Buffer ■ Smoother ■

bms 16s

Abstract: SWBT13 UT1553BCRTM ta306
Contextual Info: UT1553 BCRTM p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553 dual-redundant Bus p p p p p programmability p DMA memory interface with 64K addressability p Internal self-test p Radiation-hardened option available for 84-lead

SWBT13

Abstract: rta2 1553b rti
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

fp6160

Abstract: rta2
Contextual Info: UT1553B BCRT p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553B dual-redundant programmability p DMA memory interface with 64K addressability p Internal self-test p Remote terminal operations in ASD/ENASD-certified Bus Controller BC and Remote Terminal

sb820m

Abstract: sb850 SB800 AMD SATA 4390h Southbridge AMD Athlon II X4 a link express amd SB800 southbridge sb800 4392H
Contextual Info: AMD SB800-Series Southbridges Register Reference Guide Publication # 45482 Revision: 3.04 Issue Date: May 2011 Advanced Micro Devices 2011 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced

Contextual Info: 1 N ICStAR O verview The IDT77201 NICStAR PCI ATM Controller is a member of IDT's family of products for Asynchronous Transfer Mode ATM networks. The NICStAR performs both the ATM Adaptation Layer (AAL) Segmentation and Reassem­ bly (SAR) function and the ATM layer protocol functions.

Contextual Info: IDT79R3710 IDT79R3740 ADVANCE INFORMATION LASER PRINTER INTEGRATED SYSTEM CONTROLLER FEATURES • Pin-Compatible System Controller with Laser Printerspecific features for the IDT R30xx family of processors • DRAM Controller - 1 - 40 MB directly, 1 - 3 banks directly

SAB82C206

Contextual Info: SIEMENS SAB 82C211 CPU/Bus Controller of Siemens PC-AT Chipset Advance Information 117 3.90 SAB 82C211 • SAB 80286 bus interface and bus control • • • CPU/AT bus state machine and bus arbitration logic • Clock generator with software speed selection logic optional independent AT

E160

Abstract: E193 MC10193 SY100E193 SY10E193
Contextual Info: Micrel, Inc. SY10E193 SY100E193 SY10E193 ERROR DETECTION/ CORRECTION CIRCUIT FEATURES SY100E193 DESCRIPTION • Hamming code generation ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E193 are error detection and correction EDAC circuits designed for use in new, high- performance

IC503

Contextual Info: MIC50395/50396/50397 Six Decade Counter / Display Decoder General Description Features The MIC50395 is an ion-implanted, P-channel MOS sixdecade synchronous up/down-counter/display driver with com pare-register and storage-latches. The counter as well as the register can be loaded digit-by-digit with BCD data.

tms 3874

Abstract: RS8228EBG RS8398 Rockwell framer" Trec Part Numbering System GR
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R S Y S T E M S RS8228 Octal ATM Transmission Convergence PHY Device datasheett PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Advance Information This document contains information on a product under development. The parametric information contains target

yg 2822

Abstract: RAS 0510 cs8221 neat Waukesha 6670 82C631 82c211 2021G 82C206 CHIPset for 80286 REG62
Contextual Info: PRELIM INARY C S 8221 NEW ENHANCED AT NEAT DATA BOOK 8 2 C 2 1 1 / 8 2 C 2 1 2 / 8 2 C 2 1 5 / 8 2 C 2 0 6 (IPC ) CHIPSet™ 100% IBM™ PC/AT Compatible New En­ hanced CHIPSet™ for 12MHz to 16MHz systems Supports 16MHz 80286 operation with only 0.5-0.7 wait states for 100ns DRAMs and 12

CT1602

Abstract: 1553B CT1999 MIL-STD-1553B direct replacement WC-40
Contextual Info: CT1999 Remote Terminal and/or Bus Controller for MIL-STD-1553B Features • Performs the Complete Dual-Redundant Remote Terminal and Bus Controller Protocol Functions of MIL-STD-1553B • Automatic Switchover to Superseding Input Commands • MIL-PRF-38534 Compliant Circuits Available

232cbe

Abstract: WJ-A35 GT-64010A R5000 GT64010
Contextual Info: Galileo Technology TM System Controller with GT-64010A Preliminary PCI Interface for R4XXX/ Revision 1.1 December 1996 R5000 Family CPUs NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Integrated system controller with PCI bus interface for

64PCS

Contextual Info: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor March 2007 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store

holt ic 6110

Contextual Info: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor February 2009 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store

holt ic 6110

Contextual Info: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor August 2008 FEATURES The HI-6110 may be configured as a Bus Controller BC , a Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor Terminal with assigned RT address. 16-bit registers store

Contextual Info: HUA L ON MICR0 ELE CTRONICS U im = = = 7= EME D • ODOOPm I HM82C215 ADDRESS/DATA BUFFER = = = Features • Bus conversion logic for 16 bit to 8 bit transfers • Parity generation/detection logic Functions • • • • Address buffers and latches Data buffers and latches.