PB7A MARKING Search Results

Contextual Info: LatticeXP Family Data Sheet Version 01.3, June 2005 LatticeXP Family Data Sheet Introduction May 2005 Advance Data Sheet Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL – SSTL 18 Class I

Contextual Info: LatticeXP Family Data Sheet Version 04.4, April 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.7, August 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

Contextual Info: LatticeXP Family Data Sheet DS1001 Version 05.0, July 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

LFXP3C-3TN144C

Abstract: LFXP6C-4FN256C 3FN3 LFXP3C-3TN100C LFXP6C-3FN256I PT36 LFXP10C-3F256I LFXP3C-4TN100C LFXP15C-5FN388C LFXP6
Contextual Info: LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

PL44A

Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.9, February 2007 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

PT15B

Abstract: LFXP20C-5FN484C
Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.9, February 2007 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

LFXP10C-4FN256C

Abstract: PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C
Contextual Info: LatticeXP Family Data Sheet Version 04.5, May 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

LFXP20C-5F256C

Abstract: LFXP20C-4F484C PT15B
Contextual Info: LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001  Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2

LFXP20C-4F484C

Abstract: PT15B
Contextual Info: LatticeXP Family Data Sheet Version 04.3, March 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: LatticeXP Family Data Sheet Version 04.0, December 2005 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: LatticeXP Family Data Sheet Version 04.2, March 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: LatticeXP Family Data Sheet Version 02.0, July 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

PT15B

Contextual Info: LatticeXP Family Data Sheet Version 04.1, February 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

LFXP20C-4F484C

Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.6, June 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

PT15B

Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.8, December 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

Contextual Info: LatticeECP/EC Family Data Sheet Version 02.0, September 2005 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported

Contextual Info: LatticeECP/EC Family Data Sheet Version 01.6, May 2005 LatticeECP/EC Family Data Sheet Introduction May 2005 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported

Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.2, December 2006 LatticeECP2/M Family Data Sheet Introduction December 2006 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic

LFE2-20E-5FN256I

Abstract: lfe2m35e-7fn484c LFE2M50E-5F484C LFE2M50E-5FN484C LFE2M50E5F484C lfe2m35e7fn484c LFE2M50E-6FN484C
Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.3, February 2007 LatticeECP2/M Family Data Sheet Introduction December 2006 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic

LFEC1E-3Tn100C

Abstract: DDR400 LFEC10 LFEC15 LFEC33 LFECP10 LFECP15 LFECP20 LFECP33 LFEC1E-3TN144I
Contextual Info: LatticeECP/EC Family Data Sheet Version 01.4, December 2004 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os

lfe2m35e7fn484c

Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.7, July 2007 LatticeECP2/M Family Data Sheet Introduction July 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic • Source synchronous standards support

sot23 Transistor marking W18

Abstract: EB29 LCM-S02002DSF LDS-A304RI POWR607 68013a PT38A sot marking code w17 SOT-23 a6 ZENER aa15
Contextual Info: LatticeXP2 Standard Evaluation Board User’s Guide February 2008 Revision: EB29_01.3 LatticeXP2 Standard Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2 Standard Evaluation Board provides a convenient platform to evaluate, test and debug user