PCI9060 68040 Search Results

93CS46

Abstract: 0x00000018 E 32.0000 C 10B5 c code for pci master
Contextual Info: PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • • • • • • • • PCI9060 bridge between Primary PCI Bus and Intel

10B5

Abstract: 93CS46
Contextual Info: Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • •

68040* part numbering

Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Contextual Info: Go to next Section: Designing a PCI Memory Board Return to Table of Contents Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _

68040

Abstract: TIP 31 Transistor
Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns PCI9060/68040 STATIC RAM READ 68040 , 4 WORDS, NO WAIT STATES [SRD4_040.TD] (07/8/95) {13.33,17.33} BCLK-30 [6.5,25] [6.5,] LA[0.31], SIZ0,1 [6.5,25] [6.5,25] TS~ [6.5,25] [6.5,] TIP~ [6.5,25] [6.5,25] R/W [2,7.5] [2,7.5]

Contextual Info: 0ns TITLE 100ns 200ns 300ns PCI9060 STATIC RAM WRITE 68040 , 4 WORDS, ONE WAIT STATE [SWR4_040.TD] (07/10/95) BCLK-30 [6.5,25] LA[2.31], SIZ0,1 [6.5,25] [6.5,25] TS~ [6.5,25] [6.5,25] [6.5,25] [6.5,25] TIP~ R/W [2,7.5] [2,7.5] SRCS~ [1,5] <14.33,> <12.67,>

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns 250ns 300n PCI9060/68040 DIRECT MASTER READ 68040 , 1 WORD [DMRD1.TD] (08/01/95) BCLK-30 [1,5] ARB STATE AIDLE A1 [6.5,23] [6.5,] BR~ [1,5] BG~ [6.5,25] [6.5,] LA[0.31], SIZ0,1 [6.5,25] [6.5,25] TS~ [6.5,25] [6.5,] TIP~ [6.5,23]

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns 250ns PCI9060/68040 DIRECT MASTER WRITE 68040 , 1 WORD [DMWR1.TD] (08/01/95) BCLK-30 [1,5] ARB STATE AIDLE A1 [6.5,23] [6.5,] BR~ [1,5] BG~ [6.5,25] [6.5,] LA[0.31], SIZ0,1 [6.5,25] [6.5,25] TS~ [6.5,25] [6.5,] TIP~ [6.5,23]

1N4148/2 pin connector sip

Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
Contextual Info: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000

0x00000010

Abstract: 0x300000C0 0x0000000b E 32.0000 C 000D 10B5 0x300000C4 0x10000000-0x2FFFFFFF
Contextual Info: PLX Technology PCI9060/68040 DEMO Memory Map 06/24/96 PCI Configuration Registers PCI CFG Offset BIT 0x00000000 0-15 0x00000002 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns 250ns 300n PCI9060/68040 DIRECT MASTER READ 68040 , 1 WORD [DMRD1.TD] (08/01/95) BCLK-30 [1,5] ARB STATE AIDLE A1 [6.5,23] [6.5,] BR~ [1,5] BG~ [6.5,25] [6.5,] LA[0.31], SIZ0,1 [6.5,25] [6.5,25] TS~ [6.5,25] [6.5,] TIP~ [6.5,23]

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns PCI9060/68040 DIRECT SLAVE STATIC RAM READ, 4 WORDS, NO WAIT STATES [DSRD4.TD] 08/01/95 <8.33,> BCLK-30 [8,20] [8,20] [8,20] [8,20] [8,20] LA[2.31], LBE[0.3] [6,16.5] [6,16.5] ADS~ [6,17] [6,17] LW/R [8,20] [8,20] BLAST~

MACH210A

Contextual Info: module busctl title ' PLX TECHNOLOGY * PROPRIETARY INFORMATION * BUSCTL: Local Bus Control MACH Engineer: DLR Product: PCI 9060/68040 Demo Board Part Number: xxx-xxxx-xxxx Revision 1.0 07-18-95 Copyright PLX Technology, 1995 ' "device declaration

MACH210A

Abstract: SR040
Contextual Info: module busctl title ' PLX TECHNOLOGY * PROPRIETARY INFORMATION * BUSCTL: Local Bus Control MACH Engineer: DLR Product: PCI 9060/68040 Demo Board Part Number: xxx-xxxx-xxxx Revision 1.0 07-18-95 Copyright PLX Technology, 1995 ' "device declaration

la1 d22

Abstract: la2 d2 timer rn0805 U0301 L16 eeprom 80960CA LD11 LD12 U0101 PCI9060 68040
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH |P8.SCH

RN0804

Abstract: PD0302 68040 93CS06 RN0801 PD0501 c14 c13 PD0201 PU0201 PU0203
Contextual Info: 1 2 ADS~ LW/R BLAST~ READYO~ TS~ TIP~ BB~ LOCK040~ PU0201 A 1 2 3 4 5 6 7 8 9 10 VCC 3 RN0801 COM IN IN IN IN IN IN IN IN IN PU0202 PU0203 PU0301 PU0302 PU0303 PU0304 PU0305 PU0306 PU0307 1 2 3 4 5 6 7 8 9 10 VCC 4 RN0802 COM IN IN IN IN IN IN IN IN IN PU0601

sr960

Abstract: MACH210A SR040
Contextual Info: module srctl title ' PLX TECHNOLOGY * PROPRIETARY INFORMATION * SRCTL: Static RAM Control MACH Engineer: DLR Product: PCI 9060/68040 Demo Board Part Number: xxx-xxxx-xxxx Revision 1.0 07-12-95 Copyright PLX Technology, 1995 ' "device declaration

ld18

Abstract: LD11 ld12 LD17 LD19 LD20 LD31 LA15 LA18 LD26
Contextual Info: 1 2 3 4 5 6 7 8 VCC LA[2.31] B LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 101 102 103 106 107 108 109 110 111 112 113 115 116 117 118 119 120 121 122 125 126

la1 d22

Abstract: La2 D22 C0301 k16 a21 LD11 LD12 LD17 LD18 LD19 68040 PST0
Contextual Info: 1 2 3 4 5 6 7 8 VCC 1 R0301 100 A 2 1 VCC C0301 22uF B PCLK BCLK2 R9 R7 T5 S6 S7 PU0301 PU0302 RSTI~ T8 T7 T6 T11 IPL0~ IPL1~ IPL2~ AVEC~ T12 S12 PD0301 PD0302 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26

TCI diode

Abstract: U0401 TIP 41 transistor LA29 LA30 16v8c
Contextual Info: 1 LA[2.31] 2 3 4 5 6 7 8 LA[2.31] LA28 LA29 LA30 LA31 U0401 BCLK3 BCLK3 A TS~ TIP~ R/W TT0 TT1 TS~ TIP~ R/W TT0 TT1 BR~ BB~ LOCK040~ BR~ BB~ LOCK040~ READYO~ SRRDY~ LHOLD BREQO READYO~ SRRDY~ LHOLD BREQO ADS~ TT0 CS9060~ TS~ BB~ R/W TT1 LOCK040~ SRRDY~ TIP~

U0401

Abstract: TCI diode 16v8c TIP 41 transistor 41 bb LA29 TCI circuit LA30 MACH210
Contextual Info: 1 2 3 PD0402 13 14 15 16 17 18 19 20 21 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 11 4 16V8C 10 NSEC INTR I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 U0402 O1 IO2 IO3 IO4 IO5 IO6 IO7 O8 19 18 17 16 15 14 13 12 I4 I3 I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O31 I/O30

C0605

Abstract: J0601 34x2 HEADER 10X2 R0607 C0602 R0601 C0604 LA17 LA12
Contextual Info: 1 2 3 4 5 6 7 8 LD[0.31] LD[0.31] LA0 LA1 LA[2.31] LA[2.31] J0601 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21

AD14

Abstract: AD12 AD-12 AD11 AD17 AD27 AD29 ACK64
Contextual Info: 1 2 3 4 5 6 7 8 A A CLK TDD VCC VCC J0701 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 REQ# AD[0.31] AD[0.31] AD31 AD29 AD27 AD25 B C/BE3# AD23 AD21 AD19 AD17 C/BE2#

PD0501

Abstract: LA12 tip 35 LA15 LA16 la1 la 11 LA10 a1023 2227B SRAM 32KX8
Contextual Info: 1 2 3 A 4 5 6 7 8 A LA[2.31] LA[2.31] LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27 B U0501 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 11 12 13 15 16