PDO10 Search Results

uv detector

Abstract: ADM1066 ADM1166 AN-698 MS-026ABC
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM AUX1 AUX2 REFIN REFOUT REFGND ADM1166 MUX Complete supervisory and sequencing solution for up to 10 supplies 16 event deep ‘Black Box’ non-volatile fault recording 10 supply fault detectors enable supervision of supplies to

Contextual Info: 19-2624; Rev 1; 5/04 10Gbps 1:16 Deserializer with Clock Recovery Features The MAX3953 is a 9.953Gbps/10.3125Gbps 1:16 deserializer with clock recovery for 10Gbps Ethernet and OC192 SONET applications. The integrated phaselocked loop PLL recovers a clock from the serial data

ADM106x

Abstract: FA58 ADM1066 AN-698 VX30 x1uv
Contextual Info: AN-698 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com Configuration Registers of ADM106x by Peter Canty INTRODUCTION The ADM106x family of fully programmable supply

2N3904

Abstract: 2N3906 ADM1063 AN-698
Contextual Info: Multisupply Supervisor/Sequencer with ADC and Temperature Monitoring ADM1063 FEATURES For more information about the ADM1063 register map, refer to the AN-698 Application Note at www.analog.com. FUNCTIONAL BLOCK DIAGRAM D1P D1N D2P D2N TEMP SENSOR REFIN REFOUT REFGND SDA SCL A1

ADM1060

Abstract: ADM1067 ADM1067ACP AN-698 CP-40 MS-026ABC
Contextual Info: Super Sequencer with Open-Loop Margining DACs ADM1067 FEATURES FUNCTIONAL BLOCK DIAGRAM REFOUT REFGND SDA SCL A1 ADM1067 VX1 VX2 VX3 VX4 VX5 A0 SMBus INTERFACE VREF EEPROM CONFIGURABLE OUTPUT DRIVERS DUALFUNCTION INPUTS PDO1 PDO2 PDO3 LOGIC INPUTS OR SFDs

ADM1065

Abstract: ADM1065ACP ADM1065ACP-REEL AN-698 MS-026ABC
Contextual Info: Super Sequencer and Monitor ADM1065 FEATURES APPLICATIONS Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies FUNCTIONAL BLOCK DIAGRAM REFOUT REFGND VREF SDA SCL A1 A0 SMBus

ADM1062

Abstract: ADM1062ACP CP-40 robin pump
Contextual Info: PRELIMINARY TECHNICAL DATA Multi- Supply Supervisor/Sequencer with Margining Control Preliminary Technical Data ADM1062 a APPLICATIONS Central Office Systems Servers/Routers Multi- Voltage System Line Cards DSP/FPGA Supply Sequencing In Circuit Testing of margined supplies

56us

Abstract: OC192 MAX3953 MAX3953UGK MAX3970 MAX3971A PDO11 VCO at 15GHZ PDO15 PDO14
Contextual Info: 19-2624; Rev 0; 10/02 10Gbps 1:16 Deserializer with Clock Recovery Features ♦ Serial Data Rate: 9.953Gbps/10.3125Gbps ♦ Clock Recovery with 1:16 Demultiplexer ♦ 0.75UIP-P High-Frequency Jitter Tolerance ♦ 16-Bit Parallel LVDS Output ♦ OIF-Compliant Parallel Interface

ADM1060

Abstract: ADM1067 AN-698 PDO11
Contextual Info: Multisupply Supervisor/Sequencer with Open Loop Margining DACs ADM1067 Preliminary Technical Data FEATURES 10 supply fault detectors enabling supervision of supplies to better than 1% accuracy 5 selectable input attenuators allow supervision: Supplies up to 14.4 V on VH

ADM1060

Abstract: ADM1064 AN-698
Contextual Info: Multisupply Supervisor/Sequencer with ADC ADM1064 Preliminary Technical Data FEATURES 10 supply fault detectors enabling supervision of supplies to better than 1% accuracy 5 selectable input attenuators allow supervision: Supplies up to 14.4 V on VH Supplies up to 6 V on VP1-4

ADM1062

Abstract: CP-40 AN-698
Contextual Info: Multisupply Supervisor/Sequencer with Margining Control and Temperature Monitoring ADM1062 Preliminary Technical Data FEATURES APPLICATIONS 10 supply fault detectors enabling supervision of supplies to better than 1% accuracy 5 selectable input attenuators allow supervision:

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM For more information about the ADM1063 register map, refer to the AN-698 Application Note at www.analog.com. Rev. A REFIN REFOUT REFGND SDA SCL A1 D1P D1N D2P D2N TEMP SENSOR VREF INTERNAL DIODE MUX Complete supervisory and sequencing solution for up to

ADM1060

Abstract: ADM1067 ADM1067ACP AN-698 CP-40 MS-026ABC ADM106x
Contextual Info: Super Sequencer with Open-Loop Margining DACs ADM1067 FEATURES FUNCTIONAL BLOCK DIAGRAM REFOUT REFGND SDA SCL A1 ADM1067 VX1 VX2 VX3 VX4 VX5 A0 SMBus INTERFACE VREF EEPROM CONFIGURABLE OUTPUT DRIVERS DUALFUNCTION INPUTS PDO1 PDO2 PDO3 LOGIC INPUTS OR SFDs

ADM1066

Abstract: AN-698
Contextual Info: Super Sequencer with Margining Control and Auxiliary ADC Inputs ADM1066 FEATURES FUNCTIONAL BLOCK DIAGRAM AUX1 AUX2 REFIN REFOUT REFGND ADM1066 MUX VREF SDA SCL A1 A0 SMBus INTERFACE 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM VX1 VX3 VX4 VX5 CONFIGURABLE

ibm thinkpad board diagram

Abstract: LFCSP-40 ADM1062 ADM1063 ADM1064 ADM1065 ADM1066 ADM1067 ADM1068 ADM1069
Contextual Info: Evaluation Kit for the ADM1062ADM1069 Super Sequencers EVAL ADM106x Preliminary Technical Data DEVICE OVERVIEW The ADM106x is a range of fully programmable supply sequencers and supervisors which can be used as complete supply management solutions in systems with multiple voltage

Contextual Info: Multisupply Supervisor/Sequencer with ADC and Temperature Monitoring ADM1063-EP FUNCTIONAL BLOCK DIAGRAM FEATURES For more information about the ADM1063 register map, refer to the AN-698 Application Note at www.analog.com. D1P D1N D2P D2N TEMP SENSOR REFIN REFOUT REFGND SDA SCL A1

Contextual Info: Super Sequencer with Margining Control and Nonvolatile Fault Recording ADM1166 FUNCTIONAL BLOCK DIAGRAM FEATURES AUX1 AUX2 REFIN REFOUT REFGND ADM1166 MUX VREF EEPROM PDO1 CONFIGURABLE OUTPUT DRIVERS LOGIC INPUTS OR SFDs (HV CAPABLE OF DRIVING GATES OF N-FET)

Contextual Info: PRELIMINARY TECHNICAL DATA Multi- Supply Supervisor/Sequencer with Margining Control Preliminary Technical Data ADM1062 a APPLICATIONS Central Office Systems Servers/Routers Multi- Voltage System Line Cards DSP/FPGA Supply Sequencing In Circuit Testing of margined supplies

VCO 10GHZ oscillator

Abstract: VCO at 15GHZ MAX3953 MAX3953UGK MAX3970 MAX3971A OC192
Contextual Info: 19-2624; Rev 1; 5/04 10Gbps 1:16 Deserializer with Clock Recovery Features The MAX3953 is a 9.953Gbps/10.3125Gbps 1:16 deserializer with clock recovery for 10Gbps Ethernet and OC192 SONET applications. The integrated phaselocked loop PLL recovers a clock from the serial data

ADM1068

Abstract: ADM1069 ADM1062 ADM1066 ADM1067
Contextual Info: AN-0997 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Ping-Pong Configuration Guide for ADM1062 to ADM1069 Devices by Naiqian Ren INTRODUCTION The ADM1062 to ADM1069 Super Sequencers are configurable supervisory/sequencing devices that offer a single-chip

KT 0803 K pin configuration

Abstract: adm1062 ADM1062ACPZ
Contextual Info: Super Sequencer with Margining Control and Temperature Monitoring ADM1062 FEATURES FUNCTIONAL BLOCK DIAGRAM DP DN REFIN REFOUT REFGND SDA SCL A1 A0 ADM1062 TEMP SENSOR VREF INTERNAL DIODE MUX SMBus INTERFACE 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM

2N3904

Abstract: 2N3906 ADM1060 ADM1063 AN-698 CP-40 sets d2n transistor npn KT 0803 K pin configuration
Contextual Info: Multisupply Supervisor/Sequencer with ADC and Temperature Monitoring ADM1063 FEATURES FUNCTIONAL BLOCK DIAGRAM D1P D1N D2P D2N REFIN REFOUT REFGND SDA SCL A1 TEMP SENSOR VREF INTERNAL DIODE A0 SMBus INTERFACE ADM1063 MUX 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM

ADM1062

Abstract: EVAL-ADM1062LFEB 2N3904 2N3906 ADM1060 AN-698 CP-40
Contextual Info: Super Sequencer with Margining Control and Temperature Monitoring ADM1062 FEATURES FUNCTIONAL BLOCK DIAGRAM DP DN REFIN REFOUT REFGND SDA SCL A1 A0 ADM1062 TEMP SENSOR VREF INTERNAL DIODE MUX SMBus INTERFACE 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM

ADM1063

Abstract: ADM1064 AN-698 MS-026ABC
Contextual Info: Super Sequencer with Voltage Readback ADC ADM1064 FEATURES FUNCTIONAL BLOCK DIAGRAM AUX1 AUX2 REFIN REFOUT REFGND ADM1064 MUX VX1 VX2 VX3 VX4 VX5 VREF 12-BIT SAR ADC SDA SCL A1 A0 SMBus INTERFACE EEPROM PDO1 DUALFUNCTION INPUTS CONFIGURABLE OUTPUT DRIVERS