PHASE LOCKED LOOP (PLL) MODULES Search Results

M2010

Abstract: M2011 "Voltage Controlled Oscillators" M2015 M2016 flurocarbon plastic PHASE LOCKED LOOP
Contextual Info: FULL SIZE D.I.L. M2010, M2015 M2011, M2016 VOLTAGE CONTROLLED OSCILLATORS HCMOS, 0° TO 70°C Phase-Locked Oscillator, 5V 10 MHz – 32.768 MHz Phase Locked Loop Oscillator These PLL sub-systems incorporate all the components required for phase locked loop

alt_iobuf

Abstract: receiver altLVDS working of pll in integrated circuit pdf document for phase Locked Loop pll lock time vhdl code for loop filter of digital PLL vhdl code for phase frequency detector for FPGA EP1S10F780C5 EP1S10F780
Contextual Info: Phase-Locked Loop ALTPLL Megafunction User Guide UG-ALTPLL-8.0 November 2009 Introduction The Phase-Locked Loop (PLL) is a closed-loop frequency-control system that compares the phase difference between the input signal and the output signal of a voltage-controlled oscillator (VCO). The negative feedback loop of the system forces

free vhdl code for pll

Abstract: CPMC440CLK DS622 UG190 virtex 5 ppc real virtex 5 fpga utilization
Contextual Info: Phase Locked Loop PLL Module(v1.00a) DS622 April 10, 2008 Product Specification Introduction LogiCORE Facts The Phase Locked Loop primitive in Virtex-5FXT parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. The Phase

Contextual Info: PI6C2402 Phase-Locked Loop Clock Driver Features Description • Clock doubler The PI6C2402 features a low-skew, low-jitter, Phase-Locked Loop PLL clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the

PI6C2402

Contextual Info: PI6C2402 Phase-Locked Loop Clock Driver Features Description • Clock doubler The PI6C2402 features a low-skew, low-jitter, Phase-Locked Loop PLL clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the

PI6C2402

Abstract: PI6C2402W
Contextual Info: PI6C2402 Phase-Locked Loop Clock Driver Features Description • Clock doubler The PI6C2402 features a low-skew, low-jitter, Phase-Locked Loop PLL clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the

100khz VCO

Contextual Info: PLL350-1590Y PLL3501590Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features    Low Phase Noise / Fast Settling Time RF Feedback SPI Bus Compatible PLL IC

PLL350-2444

Contextual Info: PLL350-2444Y PLL3502444Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features    Low Phase Noise / Fast Settling Time RF Feedback SPI Bus Compatible PLL IC

cmos vco ic

Contextual Info: PLL350-1960Y PLL3501960Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features    Low Phase Noise / Fast Settling Time RF Feedback SPI Bus Compatible PLL IC

1090mhz oscillator

Contextual Info: PLL350-1120Y PLL3501120Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features    Low Phase Noise / Fast Settling Time RF Feedback SPI Bus Compatible PLL IC

Contextual Info: PI6C2402 Phase-Locked Loop Clock Driver Features Description • 2X CLK_IN on CLK_OUT The PI6C2402 features a low-skew, low-jitter, phase-locked loop PLL clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the

Contextual Info: PI6C2402 Phase-Locked Loop Clock Driver Features Description • 2X CLK_IN on CLK_OUT The PI6C2402 features a low-skew, low-jitter, phase-locked loop PLL clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the

Contextual Info: PI6C2402 Phase-Locked Loop Clock Driver Features Description • 2X CLK_IN on CLK_OUT The PI6C2402 features a low-skew, low-jitter, phase-locked loop PLL clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the

Contextual Info: PLL350-265Y PLL350-265Y 5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time RF Feedback PLL IC  SPI Bus Compatible 

Contextual Info: PLL350-1842Y PLL3501842Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time  SPI Bus Compatible  Frequency: 1805MHz to

Contextual Info: PLL400-1950AY PLL4001950AY5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL400, 15.24mm x 15.24mm x 3mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time  SPI Bus Compatible  Frequency: 1900MHz to

Contextual Info: PLL350-1260Y PLL3501260Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time  SPI Bus Compatible  Frequency: 1230MHz to

Contextual Info: PLL350-2444Y PLL3502444Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time  SPI Bus Compatible  Frequency: 2344MHz to

AL-N11

Abstract: C6000 SPRU189 SPRU190 TMS320C6000 ALN11 sys10 ALN10
Contextual Info: TMS320TCI648x DSP Software-Programmable Phase-Locked Loop PLL Controller User's Guide Literature Number: SPRU806 December 2005 2 SPRU806 – December 2005 Contents Preface . 5

Contextual Info: PLL400-1550Y PLL4001550Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL400, 15.24mm x 15.24mm x 3mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time Reference In Data, Clock, Enable, LD RF Feedback

Contextual Info: PLL350-1120Y PLL3501120Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time Reference In Data, Clock, Enable, LD RF Feedback

Contextual Info: PLL350-1590Y PLL3501590Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL350, 20.32mm x 14.78mm x 3.91mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time  SPI Bus Compatible  Frequency: 1560MHz to

Contextual Info: PLL400-1500Y PLL4001500Y5V NARROWBAND PHASELOCKED LOOP 5V NARROWBAND PHASE-LOCKED LOOP Package: PLL400, 15.24mm x 15.24mm x 3mm PLL Synthesizer Block Diagram Features  Low Phase Noise / Fast Settling Time  SPI Bus Compatible  Frequency: 1450MHz to

C6000

Abstract: TMS320C6000 0R015 SPRU733
Contextual Info: TMS320C672x DSP Software-Programmable Phase-Locked Loop PLL Controller Reference Guide Literature Number: SPRU879A May 2005 2 SPRU879A – May 2005 Contents Preface . 5