PHN100 Search Results

Contextual Info: CDCM7005 www.ti.com SCAS793B – JUNE 2005 – REVISED OCTOBER 2005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER GND GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND GND GND GND

CDCM7005HFG-V

Abstract: smd y1a
Contextual Info: CDCM7005-SP www.ti.com . SGLS390A – JULY 2009 – REVISED AUGUST 2009 3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND

CDCM61002RHBR

Contextual Info: CDCM61002 www.ti.com. SCAS870 – FEBRUARY 2009 Two Output, Integrated VCO, Low-Jitter Clock Generator

Contextual Info: CDCM61002 www.ti.com SCAS870C – FEBRUARY 2009 – REVISED FEBRUARY 2010 Two Output, Integrated VCO, Low-Jitter Clock Generator Check for Samples: CDCM61002 FEATURES 1 • 2 • • • • • • • • • • • One Crystal Reference Input Including 24.8832

CDCLVD2104RHDR

Contextual Info: CDCLVD2104 www.ti.com SCAS903A – JUNE 2010 – REVISED AUGUST 2010 Dual 1:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2104 FEATURES 1 • • • • • • • • • • • • Dual 1:4 Differential Buffer Low Additive Jitter <300 fs, RMS in

ACS9510

Abstract: icp multiplexer 24 pin ACS8510 ACS8520 ACS8522 ACS8525 ACS8530 ACS8947T QFN48
Contextual Info: ACS8947T JAM PLL Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path COMMUNICATIONS ADVANCED COMMS & SENSING Introduction FINAL Features The ACS8947T JAM PLL is a general pupose, Integer N, jitter-attenuating, differential phase-locked loop for

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685A − DECEMBER 2002 − REVISED FEBRUARY 2003 D High Performance 1:5 PLL Clock D D D D D D D D D D D D D D D Synchronizer Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock

Contextual Info: CDCM1804 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER SCAS697 – JULY 2003 D Distributes One Differential Clock Input to VSS VDD0 Y0 Y0 VDD0 S1 24 23 22 21 20 19 15 Y1 VDDPECL 5 14 VDD1 VBB 6 13 VDD3 12 4 Y3 Y1 IN VDD2 IN 11

Contextual Info: CDCM7005-SP www.ti.com SGLS390E – JULY 2009 – REVISED AUGUST 2012 3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND JITTER CLEANER Check for Samples: CDCM7005-SP FEATURES 1 • • • • • • • • VCC RESET or HOLD Y4A Y4B GND

5962-0723001VXC

Abstract: CDCM7005-SP TRF3750 CDCM7005HFG-V T0060 CDCM7005 TCO-2111 CDCM7005HFG
Contextual Info: CDCM7005-SP www.ti.com . SGLS390A – JULY 2009 – REVISED AUGUST 2009 3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND

Contextual Info: CDCLVD2104 www.ti.com SCAS903A – JUNE 2010 – REVISED AUGUST 2010 Dual 1:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2104 FEATURES 1 • • • • • • • • • • • • Dual 1:4 Differential Buffer Low Additive Jitter <300 fs, RMS in

CDCLVD1204

Contextual Info: CDCLVD1204 www.ti.com SCAS898A – MAY 2010 – REVISED JUNE 2010 2:4 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1204 FEATURES DESCRIPTION • • The CDCLVD1204 clock buffer distributes one of two selectable clock inputs, IN0, IN1 , to 4 pairs of

Space Qualified VCXO

Contextual Info: CDCM7005 www.ti.com . SCAS793D – JUNE 2005 – REVISED AUGUST 2009 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

QFN PACKAGE thermal resistance

Abstract: T006001 CDCM7005 TCO-2111 16-Div
Contextual Info: CDCM7005 www.ti.com SCAS793C – JUNE 2005 – REVISED DECEMBER 2007 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER FEATURES 1 • GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND

Contextual Info: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in

Contextual Info: CDCLVD1212 www.ti.com SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 2:12 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1212 FEATURES 1 • • • • • • • • • • • • 2:12 Differential Buffer Low Additive Jitter: <300 fs RMS in

crystal 26 Mhz package 5032

Abstract: CDCM61001 CDCM61001RHBR CDCM61001RHBT QFN-32 TSX-5032
Contextual Info: CDCM61001 www.ti.com. SCAS869B – FEBRUARY 2009 – REVISED JULY 2009 One Output, Integrated VCO, Low-Jitter Clock Generator

Contextual Info: CDCM7005 www.ti.com SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER Check for Samples: CDCM7005 FEATURES 1 • GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_

Contextual Info: CDCM7005 www.ti.com SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER Check for Samples: CDCM7005 FEATURES 1 • GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_

MUX21

Abstract: CDC7005 MUX22
Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685E − DECEMBER 2002 − REVISED NOVEMBER 2004 D High Performance 1:5 PLL Clock D D D D D D D D D D D D D D D Synchronizer Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock

Contextual Info: CDC7005 3.3ĆV HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685I − DECEMBER 2002 − REVISED APRIL 2006 D High Performance 1:5 PLL Clock D D D CTRL_ CLK CTRL_ DATA CP_OUT OPA_IN 7 8 OPA_IP OPA_OUT STATUS_ LOCK GND GND GND GND C I_REF GND AVCC

CDCM7005-SP

Abstract: T0060 CDCM7005 22N10
Contextual Info: CDCM7005 www.ti.com . SCAS793D – JUNE 2005 – REVISED AUGUST 2009 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

d2102

Contextual Info: CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 Dual 1:2 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2102 FEATURES 1 • • • • • • • • • • • • Dual 1:2 Differential Buffer Low Additive Jitter <300 fs RMS in 10-kHz to