PK1001 Search Results

Contextual Info: CMOS DUAL SyncFlFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 FEATURES: • The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs • The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs • The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18

Contextual Info: | CMOS Bus-Matching SyncFlFO 256 x 36, 512 x 36,1,024 x 36 dt PRELIMINARY ¡DT723633 IDT723643 Integrated D ev ic e Techno logy, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

Contextual Info: Integrated Device Technology, Inc. 64K x 32, 3.3V SYNCHRONOUS SRAM WITH PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER FEATURES: • 64K x 32 m em ory configuration • Supports high perform ance system speed - up to 100 MHz 5 ns C lock-to-D ata Access

Contextual Info: In te g ra te d D e v iz e T e c h n o lo g y , l i e . 64K x 32, 3.3V SYNCHRONOUS SRAM WITH PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER, SINGLE CYCLE DESELECT FEATURES: • 64K x 32 m em ory configuration • Supports high system speed: -4 4ns clock access tim e 133 MHz

INTEGRATED DEVICE TECHNOLOGY 71V432

Contextual Info: 32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V432 processor interfaces. The pipelined burst architecture provides costeffective 3-1-1-1 secondary cache performance for processors up to

body marking MCL

Abstract: IDT77155 IDT77V400 IDT77V500 IDT77V550 IDT79R36100 IDT79RV3041 IDT79RV4640 PN100-1 osam marking code
Contextual Info: SWITCHStARTM PRELIMINARY ATM CELL BASED IDT77V500 1.24Gbps NON-BLOCKING INTEGRATED SWITCH CONTROLLER Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip controller for IDT77V400 Switching Memory One IDT77V500 and one IDT77V400 form the core required

Contextual Info: 128K x 36, 3.3V Synchronous IDT71V546  Feature, SRAM with ZBT Burst Counter and Pipelined Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz

Contextual Info: SWITCHStAR ATM CELL BASED NON-BLOCKING SINGLE CHIP PRELIMINARY IDT77V500 SWITCH CONTROLLER without derating for larger switch configurations • Industrial temperature range -40° C to +85° C available • S ingle+3.3V ± 0.3V power supply • Available in a 100-pin Thin Plastic Quad Flat Pack

chn 808

Contextual Info: UtopiaFIFO PRELIMINARY INFORMATION 4-Port 128 x 9 x 4 Multiplexer-FIFO IDT77305 FEATURES: • M axim um through put per device o ver 1,4Gbps • Four Independent Input 128 x9 FIFO Q ueues • In a building blo ck configuration m ultiple input channels

Contextual Info: PRELIMINARY 128K x 36, 3.3V SYNCHRONOUS SRAM IDT71V547 WITH ZBT FEATURE, BURST COUNTER AND FLOW-THROUGH OUTPUTS D ev ice T ech n ology , l i e . FEATURES: • 128K x 36 memory configuration, flow-through outputs. • Supports high performance system speed -1 0 0 MHz

Contextual Info: 128K x 36, 3.3V SYNCHRONOUS SRAM WITH ZBT FEATURE, BURST COUNTER AND PIPELINED OUTPUTS PRELIMINARY IDT71V546 I n te g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • 128K x 36 memory configuration, pipelined outputs • Supports high performance system speed -1 3 3 MHz

Contextual Info: Integrated Devile Technology, lie. CMOS TRIPLE BUS SyncFIFOT WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 FEATURES: • Two independent FIFOs 64 X 36 storage capacity each buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C

IDT71V632

Abstract: sram with address counter
Contextual Info: 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ with full support of the Pentium and PowerPC™ processor interfaces. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz.

IDT71V633

Contextual Info: 64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect IDT71V633 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 32 memory configuration Supports high performance system speed Commercial: — 11 11ns Clock-to-Data Access 50 MHz

IDT71V433

Abstract: pin diagram for core i3 processor
Contextual Info: 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs IDT71V433 Features ◆ ◆ ◆ ◆ ◆ ◆ 32K x 32 memory configuration Supports high performance system speed: Commercial and Industrial: — 11 11ns Clock-to-Data Access 50MHz — 12 12ns Clock-to-Data Access (50MHz)

Contextual Info: 128K x 36, 3.3V Synchronous IDT71V546  Feature, SRAM with ZBT Burst Counter and Pipelined Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz

Contextual Info: 128K x 36, 3.3V Synchronous IDT71V546  Feature, SRAM with ZBT Burst Counter and Pipelined Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz

71V632

Abstract: IDT71V632
Contextual Info: 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V632/Z with full support of the Pentium and PowerPC™ processor interfaces. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz.

Contextual Info: 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V632 with full support of the Pentium and PowerPC™ processor interfaces. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz.

AZ 280 chip

Abstract: IDT71V632
Contextual Info: Integrated Device Technology, Inc. 64K x 32, 3.3V SYNCHRONOUS SRAM WITH 3.3V/2.5V PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER FEATURES: • 64K x 32 memory configuration • Supports high performance system speed - up to 133 MHz 4.5 ns Clock-to-Data Access in Pipelined Mode

71V547

Abstract: IDT71V547
Contextual Info: 128K X 36, 3.3V Synchronous IDT71V547S/XS SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 memory configuration, flow-through outputs Supports high performance system speed - 95 MHz

Contextual Info: 32K x 36, 3.3V SYNCHRONOUS BURST SRAM WITH FLOW-THROUGH OUTPUTS PRELIMINARY IDT71V537 Integrated Device Technology, Inc. FEATURES: • 32K x 36 memory configuration • Supports high performance system speed - up to 75 MHz 8 ns Clock-to-Data Access • LBO input selects interleaved or linear burst mode

PBSRAM

Abstract: IDT71F432 IDT71F432S66 IDT71F432S75
Contextual Info: FEATURES: • • • • • • • • • • Uses IDT's Fusion Memory technology 66 and 75 MHz speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write 3-1-1-1-1-1-1-1. extended pipelined operation Refresh overhead consumes less than 0.5% of cycles

IDT71V633

Contextual Info: 64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect IDT71V633 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ tecture provides cost-effective 2-1-1-1 performance for processors up to 50 MHz. The IDT71V633 SRAM contains write, data-input, address and control