PLA MACROCELLS Search Results

MC15

Abstract: PZ5032 pal 16 macrocells pla macrocells SIGNAL PATH DESIGNER BUT30
Contextual Info: Philips Semiconductors CoolRunner architecture overview array while the PLA array consist of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array while the PLA array provides increased product term density.

Contextual Info: bOE D • D2S7S2b G033Qüfl 3fl7 ■ AMD2 ADV niCRO PLA/PLE/ARRAYS COM’L: -12/15/20 "T- ll-Q r] MIL: -20 MACH110-12/15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS ■ 44 Pins ■ 38 Inputs ■ 32 Macrocells

THX 201

Abstract: 26V12 PA7536 I326
Contextual Info: PA7536 PEEL Array Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried

Contextual Info: AÎ>V MICRO PLA/PLE /AR RAYS b4E D □25752b 003357Ö 2D5 IND: -25/30 il PALLV16V8Z Family Low-Voltage, Zero-Power, 20-Pin EE CMOS Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC

THX 201

Abstract: PA7540P-15 GAL6002 PA7540 a7540j A7540
Contextual Info: PA7540 PEEL Array Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried

AmPAL23S8-30

Contextual Info: A DV MICRO PLA/PLE/ARRAYS , Tt. D e | 02S7S2t, 0 0 2 7 2 2 7 1 T -V 4 -/3 -V 7 AmPAL23S8 20-Pin IMOX PAL Device-Based Sequencer Distinctive C haracteristics • • • • • 14 Registers - 4 Output Logic Macrocells OLMs - 4 Output Registers - 6 Buried State Registers (BSRs)

Contextual Info: ADV MICRO PLA /PLE/A RRAY S PRELIM IN ARY b4E » □ SS752b □Ü337flcl ISS IAMDS IND: -25 PALLV22V10Z-25 Low-Voltage, Zero-Power 24-Pin EE CMOS Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC

ICT Peel

Abstract: PA7540S-15 GAL6002 PA7540
Contextual Info: Commercial/Industrial PA7540 PEEL Array Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried

Contextual Info: Commercial/Industrial PA7540 PEEL Array Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried

pal22v10

Abstract: stag ppz
Contextual Info: ADV MICRO PLA/PLE/ARRAYS 4ÔE J> COM’L 025752b DG3207Ö T -<3 P A L 2 2 V 1 0 -7 7.5 ns 24-Pin TTL Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • ■ ■ ■ 7.5 ns propagation delay and 91 MHz fMAX 10 macrocells programmable as registered or

Contextual Info: Commercial/Industrial PA7540 PEEL Array Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried

"Programmable Electrically Erasable Logic Array"

Contextual Info: Commercial/Industrial PA7540 PEEL Array Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried

LT016

Abstract: LT08 YD-350 ecu schematics AIX200 LT08C LBd8 AIX2024 COF2001
Contextual Info: ADV faCRO PLA/PLE/ARRAYS 13E D Am353 b oas?sat, aoaasib 1 1 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced

7c361

Contextual Info: M CY7C361 CYPRESS SEMICONDUCTOR Features • High speed: 125-MHz state machine output generation — Token passing — M ultiple, concurrent processes — Multiway branch or join Ultra High Speed State Machine EPLD — Skew-controlled OR output array — Outputs are sum o f states like PLA

Contextual Info: ADV MI CRO PLA/PLE/ARRAYS 13e o I 0ES7SEti a o a a iia a I Advance-Information P A L C E 2 4 V jp i 1 O H Advanced Micro Devices - 1 5 / 2 5 EE CMOS Versatile Programmable Array Logic DISTINCTIVE CHARACTERISTICS • ■ Electrically erasable CMOS technology

Contextual Info: ADV NICRO PLA/PLE/ARRAYS PA LC E 29M 16H - 25/35 13E 0 > 0E5752t □ O S A I S' I I 24-Pin E2-Based CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS High-performance semicustom logic replace­ ment; Electrically Erasable E2 technology allows rep ro g ra m m a b le

xc2064 pcb

Abstract: Y148 K6A60 XC-2064-50 XC2018-50
Contextual Info: ADV M C R O PLA/PLE/ARRAYS „ E „ | H n 5 a g | Logic Cell Array M 2 0 6 4 /M 2 0 1 8 Features/Benefits USER l/Os CONFIG­ URATION PROGRAM BITS • Completely reconflgurable by the user In the final system LOGIC CONFIG­ CAPACITY URABLE PART NUMBER (USABLE

ALU IC 74181 circuit diagram

Abstract: TTL 74189
Contextual Info: ]>î| G5S7S5b DOEIOOB 1 ADV MICRO P LA /P LE/A RR AY S 7h 0 2 5 7 5 2 6 ADV MICRO PLA/PLE/ARRAYS 76C 21003 T-42-11-09 A m 7 2 2 a Q 2200 Gate HCMOS Evaluation Macrocell Array & ¡ it PRELIMINARY > 3 •Vj DISTINCTIVE CHARACTERISTICS Delay measurement block:

LBD8

Abstract: lt08 LT016
Contextual Info: ADV KICRO PLA /P LE /A R R A YS 13E D 1 05S7Sat. Q O a flà lt *1 I Am3530 Mixed ECL/TTL I/O Mask-Programmable Gate Array > 3 DISTINCTIVE CHARACTERISTICS GO 01 Integrated up to 410 ECL-equivalent gates in a 24-pin slim DIP , to eliminate "g lu e " logic, resulting in reduced

palce16v8 programming algorithm

Contextual Info: 5TE D • 02 57 5 2 b 00 32 2 7 1 510 MANDE ADV MICRO PLA/PLE/ARRAYS COM’L: H-7/10/15/25, Q-15/25 -_ MIL: H-10/15/20/25 PALCE16V8 Family AdvS EE CMOS 20-Pin Universal Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS ■ ■ Pin, function and fuse-map compatible with all

Contextual Info: ADV MI CRO PLA/PLE/ARRAYS 2öE D 1 Ë E ÎS I1 1 I COM’L: H-10/15/25, Q-15/25 P A L C E 1 6 V 8 02S7SEb o o s m u IAMDS 1 MIL: H-20/25 T -4 6 -T 9 -0 7 Advanced Micro Devices EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS •

P5C032-40

Abstract: P5C032-35 p5C032-30 5c03235 16H8 intel PLD 5C032
Contextual Info: ¡rit !, 5C032 8-MACROCELL CMOS PLD • High-Density, Low-Power Replacement for SSI & MSI Devices and Bipolar PLDs ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs ■ Eight Macrocells with Programmable I/O Architecture ■ tpo = 30 ns (max), 43.5 MHz Pipelined,

COOLRUNNER-II examples

Abstract: XC9500 pinout CP132 CPLD XC2C64 from Xilinx CoolRunner-II family
Contextual Info: R CoolRunner-II CPLD Family DS090 v1.0 January 3, 2002 Advance Product Specification Features • • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells

XAPP393

Abstract: DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table
Contextual Info: R CoolRunner-II CPLD Family DS090 v1.7 October 2, 2003 Preliminary Product Specification Features • • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells