PLCC32P Search Results

high level block diagram for asynchronous FIFO

Abstract: DIP28-W-300 LH540202 LJH540202
Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based onfully-staticCMOSdual-portSRAM tech­ nology, capable of storing up to 1024 nine-bit words. It

32-PIN

Abstract: LH540202
Contextual Info: SHARp ^ blE ]> • i w ^ / m o m ô i a Q ? DG1D1MD 6Bb « S R P J /no p r e li m i n a r y I / U 4 - CMOS 5 1 2 x 9 / 1 0 2 4 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-ln, First-Out mem­

LH5498

Contextual Info: LH5498 FEATURES • • Fast Access Times: 15/20/25/35/50/65/80 ns PIN CONNECTIONS 32-PIN PDIP TOP VIEW W C Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags

Contextual Info: LH5492 4 K x 9 Clocked FIFO FEATURES status output signals are synchronized to these clocks, to simplify system design. The input and output ports oper­ ate altogether independently of each other, except when the FIFO becomes either totally full or else totally empty.

CMOS ASYNCHRONOUS FIFO 32 PIN

Abstract: LH540202 32-PIN
Contextual Info: LH540202 CMOS 1024 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 1024 nine-bit words. It

LH5492

Abstract: 32-PIN
Contextual Info: LH5492 FEATURES • Fast Cycle Times: 25/30/35 ns Frequency: 40/33/28.5 MHz • Parallel Data In; Parallel Data Out • Two Read Enable Inputs and Two Write Enable Inputs, Sampled on Rising Edge of the Appropriate Clock • Fast-Fall-Through Time Internal Architecture Based

LH540203

Abstract: LH5498 32-PIN
Contextual Info: LH540203 CMOS 2048 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 2048 nine-bit words. It

Contextual Info: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing The LH540204 is a FIFO First-In, First-Out memory

Contextual Info: LH5496/96H FEATURES • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 5 1 2 x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable-in Width and Depth W C 1• 28 —I ^ c c

Contextual Info: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing The LH540204 is a FIFO First-In, First-Out memory

Contextual Info: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns The LH540204 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 4096 nine-bit words. It

MD 7144

Abstract: lh5494
Contextual Info: LH5494/ 4K X9 Serial-toParallel FIFO input and output ports respectively. However, these ‘clocks' also may be aperiodic, asynchronous ‘demand’ signals: they do not need to be synchronized with each other in any way. Almost all control input signals and

Contextual Info: PRELIMINARY LH540203 CMOS 2048 X 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION FEATURES • Fast Access Times: 15/20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely

Contextual Info: CMOS 1 K x 9 FIFO TO P V IEW 28-PIN PDIP • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write w C 1« 28 Dg C 2 27 □ d3 3 26 □ d5 C o • Fast Access Times: 15 720/25/35/50/65/80 ns PIN CONNECTIONS LJ < o FEATURES d. o2 C 4 25 ZI De

Contextual Info: LH5493 FEATURES • Fast Cycle Times: 30/35 ns Frequency: 33/28.5 MHz • Parallel Data In; Serial Data and/or Parallel Data Out • Serial Input and Serial Shift Capability in Output Register, for Long-Word-Length Parallel-to-Serial Operations • Read Enable input and Two Write Enable

Contextual Info: LH5499 FEATURES CMOS 4K x 9 FIFO PIN CONNECTIONS • Fast Access Times: 20/25/35/50/65/80 ns • Full CMOS Dual Port Memory Array W C • Fully Asynchronous Read and Write • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Read Retransmit Capability

QE RTB

Abstract: lh5497
Contextual Info: LH5497 FEATURES • • • • • • Fast Access Times: 15/20/25/35/50/65/80 ns PIN CONNECTIONS 28-PIN PDIP TOP VIEW w C Full C M O S Dual Port Memory Array Fully Asynchronous Read and Write Expandable in Width and Depth 1• 28 H v cc Dg C 2 27 □ d4

Contextual Info: PRELIMINARY LH540203 C M O S 2048 X 9 A sy n ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 2048 nine-bit words. It

Contextual Info: LH540201/02 PRELIMINARY CMOS 512 x 9 /1 0 2 4 x 9 A syn ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-In, First-Out mem­ ory device, based on fully-static CMOS dual-port SRAM

Contextual Info: LH5497/97H FEATURES • • Fast Access Times: 15 720/25/35/50/65/80 ns CMOS 1 K x 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW WC Full CMOS Dual Port Memory Array 1• 28 □ V CC DS C 2 27 □ d4 D a li 3 26 3 d5 • Fully Asynchronous Read and Write Dj C

32PLCC

Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing

hcl l54

Abstract: t538 LM3935 TXC7A dr3 c502 7A14300038 T596 quanta b30 c300 - 1 South Bridge ALI M1535
Contextual Info: 5 4 3 2 1 Model MODEL REV MK3 M/B BOARD 1A 2A CHANGE LIST MK3 M/B BOARD Page FM 1 1A 2 3A PAGE 8 Layout change add R420,R423 for U25 OSC32K,Y3 BOM del 3 3B PAGE11 Layout change add C648 for HWPG,U5 and TC1&D2 BOM del First Release PAGE 2 Layout change add U37,R411,R412,R413,R414,R415,C647 for AMD recommand

ICS954206A

Abstract: realtek 8110 cpu c644 100v 27p 31CT3MB0015 Socket AM2 quanta 31CT3MB0031 Quanta CT3 A06402 quanta ct1
Contextual Info: 5 4 3 2 1 Model MODEL REV CT3/5 MB D 1A 31CT3MB0015 31CT3MB0031 CHANGE LIST Page PAGE 2 - Enable CLK48M from clokc generator for the PLL circuit of 7411, and disable the ocsillator circuit of PCI7411 PLL. PAGE 3 - Remove H/W shutdown circuit that supported ADM1032.

SW1010C

Abstract: tipl22 b10 45g BD3 c502 diode "Z3M" PA6 MD35 quanta CH2506E PA6 MD40 "Digital isolation Barrier" modem
Contextual Info: 5 4 3 2 1 ET2T SYSTEM BLOCK DIAGRAM PCI .CLOCK CK-GEN AMD Processor Socket A DC/DC ICS950902 P3,4 Max1632,Max1717 P2 D 5V,3V,CPUCORE VCC etc. P23 INTA#(VGA) DDR DIMM Twister-K NB VT8372 S3 Savage8 P11 CRT P16 LCD/INV CONN LVDS P17 H/W MONITOR 200/266MHZ