PLL FOR 144 MHZ Search Results

M2032

Abstract: M513 MAVC-060000-100144
Contextual Info: Synthesizer , SMT Fixed Frequency, 144 MHz MAVC-060000-100144 Rev: A Features ♦ ♦ ♦ ♦ ♦ RoHS Compliant Fully Integrated VCO, PLL, Loop Filter High Performance, Low Cost Miniature SMT Package LSM6 Includes microcontroller for PLL programming Description

Contextual Info: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement

Contextual Info: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement

3M Touch Systems

Contextual Info: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement

CY7C1665KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C1663KV18, CY7C1665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement

Contextual Info: CY7C1663KV18/CY7C1665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement

3M Touch Systems

Contextual Info: CY7C1663KV18, CY7C1665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement

Contextual Info: Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s ROS-1000PV+ 900 to 1000 MHz Features •฀low฀phase฀noise,฀-144฀dBc/Hz฀at฀1฀MHz,฀typ. •฀linear฀tuning,฀27-38฀MHz/V฀typ. •฀aqueous฀washable CASE STYLE: CK605

Contextual Info: NON-CATALOG Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s ROS-1000PV 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: Contact Sales Dept.

Contextual Info: Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s ROS-1000PV+ 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49

Contextual Info: Surface Mount ROS-1000PV+ ROS-1000PV Voltage Controlled Oscillator 5V Tuning for PLL IC's 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49

ROS-1000PV

Abstract: 1000PV PL-012
Contextual Info: ROS-1000PV+ ROS-1000PV Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49

PL-012

Abstract: ROS-1000PV
Contextual Info: ROS-1000PV+ ROS-1000PV Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49

PL-012

Abstract: ROS-1000PV
Contextual Info: ROS-1000PV+ ROS-1000PV Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49

eMIOS channel is set up to drive the eTPU

Contextual Info: SPC563M60L5 SPC563M60B2 32-bit Power Architecture based MCU for automotive powertrain applications Preliminary Data Features • Fully static operation, 0 MHz - 80 MHz plus 2% frequency modulation - 82 MHz ■ -40 °C to 150 °C junction temperature ■

3.686 MHZ

Abstract: ICD2028 23967 IC 40007
Contextual Info: ICD2028 PC Motherboard Clock Generator Features Functional Description • Eight independent dock outputs handle all clocking requirements for personal computer motherboards • CPU clock frequency range: 10 MHz to 100 MHz with user-defined duty cycle • Four user-configurable outputs

TFBGA_78

Contextual Info: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights High Performance PCI Controller • 33/66 MHz 32-bit PCI Target

LVCMOS25

Abstract: FAR Family C4 Series P-Q type
Contextual Info: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights High Performance PCI Controller • 33/66 MHz 32-bit PCI Target

k3934

Abstract: PH90 STM-16 PH180
Contextual Info: 2.5 Gbit/s Clock and Data Recovery Circuit GD16506 Advance Information General Description Features The 155 MHz output clock is maintained within 500 ppm tolerance even in absence of data. The GD16506 is a high performance monolithic integrated 2.2 to 2.7 Gbit/s

pH 4 n

Abstract: eea 2231 PH90 STM-16 bang bang phase detector ph-180
Contextual Info: 2.5 Gbit/s Clock and Data Recovery Circuit GD16506 Advance Information General Description Features The 155 MHz output clock is maintained within 500 ppm tolerance even in absence of data. The GD16506 is a high performance monolithic integrated 2.2 to 2.7 Gbit/s

tfBGA PACKAGE thermal resistance

Contextual Info: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights High Performance PCI Controller • 33/66 MHz 32-bit PCI Target

LVCMOS25

Contextual Info: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller

U4257bm

Abstract: U4257 A2401
Contextual Info: Features • • • • • • • • • • • • AM/FM Tuner Front End with Integrated PLL AM Up-conversion System AM-IF: 10.7 MHz FM Down-conversion System (FM-IF: 10.7 MHz) IF Frequencies up to 25 MHz Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz

U4257bm

Abstract: U4257 U4257B 4528D S391D FM receiver integrated circuit automatic tune sw1 band sw2 receiver am mw B123 B140 B141
Contextual Info: Features • • • • • • • • • • • • AM/FM Tuner Front End with Integrated PLL AM Up-conversion System AM-IF: 10.7 MHz FM Down-conversion System (FM-IF: 10.7 MHz) IF Frequencies up to 25 MHz Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz