PLL LOCK TIME Search Results

AN237 equivalent

Abstract: SMY02 5V996 AN-237 IDT5T2010 5T9110 5T9820 5T9821 5T9890 5T9891
Contextual Info: APPLICATION NOTE AN-237 PLL LOCK INDICATOR APPLICATION NOTE AN-237 PLL LOCK INDICATOR INTRODUCTION A PLL lock detector is implemented on the following device families: TurboClockII, TurboClockII Plus, TeraClock and Programmable Clock. The output of the lock detector is available on the LOCK pin. The lock circuitry

ICS1523

Abstract: Integrated Circuit PLL 1523AA3
Contextual Info: Integrated Circuit Systems, Inc. ICS1523 1523 Document Type: Application Alert Document Stage: Release Solution for Long Delays between Resetting PLL and PLL Lock How to use ACK cycles to optimize PLL lock time Problem: In some applications, the screen displays incorrect data when the phase-locked loop (PLL) is reset. When

2510C

Abstract: 30PF CSP2510C IDTCSP2510C CY923
Contextual Info: IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE IDTCSP2510C 3.3 PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: lock loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK)

Contextual Info: IDTCSP2510B 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE IDT74CSP2510B 3.3 PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: lock loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK)

LMX2541

Abstract: LMK03001C LMX2485 LMX2531 4TH ORDER MODULATOR
Contextual Info: PLL Fundamentals Part 2: PLL Behavior Dean Banerjee Overview • General PLL Performance Concepts – – – – PLL Loop Theory Lock Time Spurs Phase Noise • Fractional PLL Performance Concepts – Generation of Fractional N Value – Fractional N Phase Noise

Contextual Info: IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: DESCRIPTION: • The CSP2510C is a high performance, low-skew, low-jitter, phase-lock loop PLL clock driver. It uses a PLL to precisely align, in both frequency

Contextual Info: July 1993 Edition 1.0 FUJITSU DATA SHEET MB1516 1.1GHz HIGH-SPEED LOCK-UP PLL FREQUENCY SYNTHESIZER FOR GSM High-speed lock-up & low noise PLL frequency synthe­ sizer for GSM Global System for Mobile Communication The Fujitsu MB1516 is aserial input phase-locked loop (PLL) frequency synthesizer with a

CSP2510D

Abstract: IDTCSP2510D
Contextual Info: IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER DESCRIPTION: FEATURES: The CSP2510D is a high performance, low-skew, low-jitter, phase-lock loop PLL clock driver. It uses a PLL to precisely align, in both frequency

MB1516

Abstract: CMOS 7-bit programmable counter ic
Contextual Info: July 1993 Edition 1,0 FUJITSU DATA SHEET MB 1 5 1 6 1.1GHz HIGH-SPEED LOCK-UP PLL FREQUENCY SYNTHESIZER FOR GSM High-speed lock-up & low noise PLL frequency synthe­ sizer for GSM Global System for Mobile Communication The Fujitsu MB1516 is aserial input phase-locked loop (PLL) frequency synthesizer with a

clock generator of computer motherboard

Abstract: 8042 "Keyboard Controller" motherboard power control circuit 8042 Keyboard Controller Am486DX2-80 8042 keyboard motherboard power on circuit 8042 Keyboard Controller program phoenix multikey Phase lock loop
Contextual Info: Phase Lock Loop PLL Clock Control Advanced Micro Devices Application Note Significant system power savings can be achieved by using the Phase Lock Loop (PLL) clock control circuit outlined in this application note with any Am486 or Am5X86 family microprocessor.

12E1

Abstract: ACS8530
Contextual Info: AN-SETS-7 PLL Configurations for ACS8530 ADVANCED COMMUNICATIONS PRELIMINARY APPLICATION NOTE Phase Lock Loop Configurations for the Semtech ACS8530 SONET and SDH SETS Device Overview This Application Note describes some examples of the ways in which the ACS8530 Phase Lock Loops PLL can be

PLL 100Mhz

Abstract: MB15E64UV XCS17 A4N1
Contextual Info: Fujitsu semiconductor Rev2.1 ASSP Sigma delta Fractional-N PLL Frequency Synthesizer 3.5GHz single PLL MB15E64UV DESCRIPTION The Fujitsu MB15E64UV includes a serial input Sigma delta Fractional Phase Locked Loop (PLL) frequency synthesizer with fast lock up function. The PLL consists of 3.5GHz sigma delta Fractional-N PLL.

F0514

Abstract: MB15E65UV
Contextual Info: Fujitsu semiconductor Rev2.0 ASSP Sigma delta Fractional-N PLL Frequency Synthesizer 2.0GHz single PLL MB15E65UV DESCRIPTION The Fujitsu MB15E65UV includes a serial input Sigma delta Fractional Phase Locked Loop (PLL) frequency synthesizer with fast lock up function. The PLL consists of 2.0GHz sigma delta Fractional-N PLL.

SMPTE-292

Abstract: ldc 2000 rev.01
Contextual Info: HDTV 1.5 Gbit/s Re-timer GD14526 Preliminary General Information Features When in lock, the digital Lock Detect Circuit LDC uses the incoming data to control the PLL. When not in lock, i.e. the VCO frequency is more than 500 ppm away from the REFCK frequency, the

CSP2510D

Abstract: IDTCSP2510D
Contextual Info: IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • • • • • • • • loop PLL clock driver. It uses a PLL to precisely align, in both frequency

Contextual Info: IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • • • • • • • • loop PLL clock driver. It uses a PLL to precisely align, in both frequency

Contextual Info: IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • • • • • • • • loop PLL clock driver. It uses a PLL to precisely align, in both frequency

2510C

Abstract: CSP2510C IDTCSP2510C
Contextual Info: IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • • • • • • • • loop PLL clock driver. It uses a PLL to precisely align, in both frequency

388915T

Abstract: 20PF FCT388915T IDT74FCT388915T MC88915T SO28-7
Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE IDT74FCT388915T 70/100/133/150 FEATURES: DESCRIPTION: − − The FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low

PC133 registered reference design

Contextual Info: Integrated Circuit Systems, Inc. DATA SHEET ICS2509C ICS2509C 3.3V Phase-Lock Loop Clock Driver 3.3V Phase-Lock Loop Clock Driver General Description Features The ICS2509C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop PLL technology to

2.1Ghz oscillator

Abstract: 1GHz PRESCALER Prescaler VCO 1ghz 900 mhz oscillator VCO 100mhz
Contextual Info: PLL Synthesizer Modules Series : PJ1, PK1 Features Low profile type Integration of VCO and PLL-IC into a compact body Meeting requirements for high speed lock up time Recommended Applications Digital cellular systems Performance Specifications, Summary Single band type

MB15F08SL

Abstract: MB15F88UL NC11 TSSOP-20
Contextual Info: Jun. 2001 Edition 3.0 ASSP Fractional-N PLL Frequency Synthesizer MB15F88UL n DESCRIPTION The Fujitsu MB15F88UL is Fractional-N Phase Locked Loop PLL frequency synthesizer with fast lock up functional. The Fractional-N PLL operating up to 2600MHz and the integer PLL operating up to 1200MHz are integrated on one

12v A spms

Abstract: Philips Capacitor 150nF 400v AC to DC smps circuit diagram pages TDA9103 1N4004 M4 free transistor BC547 temperature IR430 27kHz to 85khz 6 PIN smps control ic about transistor bc547
Contextual Info: TDA9103 DEFLECTION PROCESSOR FOR MULTISYNC MONITOR . . . . . . . . . . . . . . HORIZONTAL DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY SELF-ADAPTIVE EX : 30 TO 85kHz X-RAY PROTECTION INPUT DC ADJUSTABLE DUTY-CYCLE INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICATION

PC133 registered reference design

Contextual Info: Integrated Circuit Systems, Inc. ICS2510C DATA SHEET ICS2510C 3.3V Phase-Lock Loop Clock Driver 3.3V Phase-Lock Loop Clock Driver General Description Features The ICS2510C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop PLL technology to