PONG Search Results

laser LED

Abstract: 680R ACS4005 ACS4050 ACS9010 TQFP44 1M preset potentiometer 3pin package
Contextual Info: ACS9010 Main Features Half duplex serial transmission. * Full duplex serial transmission in Ping Pong systems. * Up to 34Mbps, E3 data rates. * Link lengths up to 25Km for full duplex ping pong . * Link lengths up to 100Km for half duplex. * Switchable PLL Clock Recovery and Data Re-Synchronisation.

CA16

Abstract: TA16 1553 SUmmit
Contextual Info: 3.0 CIRCULAR BUFFERS and PING-PONG OPERATIONS 3.1 Data Management The SµMMIT RTE circular buffer simplifies the software service of remote terminals implementing bulk or periodic data transfers. The Enhanced SµMMIT architecture allows the user to select one of two circular buffer modes. The user selects the

TDS714L

Abstract: modulator 26MHz AD8302 spur spur free fractional PLL pong VCO190-1843T ADF4193 DCS1800 GSM900 TRANSISTOR SDM M6
Contextual Info: Low Phase Noise, Fast Settling PLL Frequency Synthesizer ADF4193 FEATURES GENERAL DESCRIPTION New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 s with phase settled by 20 μs 0.5° rms phase error at 2 GHz RF output

"USB" peripheral

Contextual Info: Features • • • • • • • USB V1.1 Compliant, 12 Mbits per second Number and Size of Endpoints Fully Parametrizable in RTL Embedded Dual Port RAM for Endpoints Suspend/Resume Logic Ping-pong Mode 2 Memory Banks for Isochronous Endpoints Compatible With an Embedded ARM7TDMI Processor

AT89C5131A-L

Contextual Info: Active Errata List • • • • • • • • • • • USB – Ping-Pong databank 1 Re-transmission Failure USB – Ping-Pong OUT Bad Reception USB – Bad Remote Wake-up Generation UART Interface – During Reception, Clearing REN may Generate Unexpected IT

Contextual Info: O K I Semiconductor MSM7503 Multi-Function PCM C O D E C GENERAL DESCRIPTION The MSM7503 is a high performance, low power CODEC LSI device integrating a 2-wire time division transmission ping-pong transmission interface function and has a basic function of

fuzzy logic library pic c code

Abstract: FUZZY pic MICROCONTROLLER pwm ultrasonic transducer polaroid source code variable speed fan controller PI fuzzy c source code xe1030 PIC FUZZY project XE0068 circuit cellar
Contextual Info: speed. In turn, the fan controlled the height of a ping-pong ball in a vertical tube. However, ping-pong did not fit the trade show's "Beach Party" theme. So, we upped the ante, replacing the pong ball with a beach ball. FEATURE ARTICLE Robert Schreiber

Contextual Info: Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer ADF4196 Data Sheet FEATURES GENERAL DESCRIPTION Fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 s with phase settled

Contextual Info: Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer ADF4196 Data Sheet FEATURES GENERAL DESCRIPTION Fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 s with phase settled

Contextual Info: Low Phase Noise, Fast Settling PLL Frequency Synthesizer ADF4193 Data Sheet FEATURES GENERAL DESCRIPTION New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 µs with phase settled

PID microcontroller

Abstract: 1766B "USB" peripheral
Contextual Info: Features • • • • • • • • USB V1.1-Compliant/12 Mbits/s Number and Size of Endpoints Fully Parametrizable in RTL Embedded Dual-port RAM for Endpoints Suspend/Resume Logic Ping-pong Mode 2 Memory Banks for Isochronous Endpoints Compatible with Any 8-bit Microcontroller

43uH

Abstract: src 0520 m
Contextual Info: 2 . Schem atic: 1. M ech anica l Dimensions: -o 6 XFMRS YYWW “° 5 PRI XF441-D0 3 o « SEC -O 4 3. E l e c t r i c a l Sp eci fications: @25°C -0.500 Max- Isolation Voltage: Turn PRI. Ratio: 1000VAC Mininnum PRI LL: 43u H M a xim u m PRI DCR: PONG. 5.12

pp1x

Contextual Info: UTMC APPLICATION NOTE Enhanced SµMMIT Ping-Pong Feature When enabling and disabling ping-ponging, the act of enabling or disabling must be observed via the acknowledge bit. If no acknowledge is seen, the user MUST make another attempt at

atmel bootloader C51

Abstract: AT89C5131A-M A04427 AT89C5131AM
Contextual Info: Active Errata List • • • • • • • • • USB – Ping-Pong databank 1 Re-transmission Failure USB – Ping-Pong OUT Bad Reception USB – Bad Remote Wake-up Generation UART Interface – During Reception, Clearing REN may Generate Unexpected IT

pulse doppler radar

Abstract: 06333 4 bit mod 16 d flip-flop VCO190-1843T d0945 circuit diagram of MOD 64 counter
Contextual Info: Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer ADF4196 Data Sheet FEATURES GENERAL DESCRIPTION Fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 s with phase settled

MSM6955

Abstract: M6955 z11h
Contextual Info: O KT sem iconductor M SM 695SGS DIGITAL LINE TRANSCEIVER The MSM6955 is a high perform ance, low power consumption type digital line transceiver LSI adopting tim e division tw o -w ire ping-pong transmission method at a line bit rate of 512Kb/s. It realizes 144Kb/s (2B + D) tw o-w ay comm unication over a single pair o f twisted w ires.

Contextual Info:  211 N. First Street 612-849-6205 Minneapolis, MN. 55401 www.soberton.com info@soberton.com PRODUCT NAME ELECTRET CONDENSER MICROPHONE PART NUMBER DIEMESION TYPE EM6050P Φ6.0x5.0mm PIN APPROVED BY CHECKED BY ISSUED BY Daniel Liu Max Pong Ryan Wei 50 100

69151 summit datasheet

Abstract: 1553 SUmmit MIL-STD-1553 terminals NA 7805 69151 summit fpga 1553B UT69151 ut69151 lxe/dxe UT63M14X MIB 30 BP
Contextual Info: ENHANCED SµMMIT FAMILY Product Handbook UTMC Microelectronic Systems Inc. 4350 Centennial Blvd. Colorado Springs, CO 80907 October 1999 I Table of Contents 1.0 INTRODUCTION 1.1 Remote Terminal Features 1.1.1 Indexing 1.1.2 Buffer Ping-Pong 1.1.3 Circular Buffers

1553 SUmmit

Abstract: ut69151 lxe/dxe UT69151 69151 summit 69151 summit datasheet 7805 smd fpga 1553B SMD MARKING CODE A20 std dual diode code A7 TI-68
Contextual Info: ENHANCED SµMMIT FAMILY Product Handbook UTMC Microelectronic Systems Inc. 4350 Centennial Blvd. Colorado Springs, CO 80907 October 1999 I Table of Contents 1.0 INTRODUCTION 1.1 Remote Terminal Features 1.1.1 Indexing 1.1.2 Buffer Ping-Pong 1.1.3 Circular Buffers

"FRACTIONAL INTERPOLATOR"

Abstract: APPLICATIONS OF mod 8 COUNTER bjt differential amplifier application circuits circuit diagram of MOD 64 counter Transistor based fm modulator ct icp multiplexer 24 pin modulator 26MHz VCO190-1843T ADF4193 DCS1800
Contextual Info: Low Phase Noise, Fast Settling PLL Frequency Synthesizer ADF4193 FEATURES GENERAL DESCRIPTION New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers 0.5 degree rms phase error at 2 GHz RF output Digitally programmable output phase

phase detector AD8302

Contextual Info: Low Phase Noise, Fast Settling PLL Frequency Synthesizer ADF4193 Data Sheet FEATURES GENERAL DESCRIPTION New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 µs with phase settled

USB V1.1 Device

Abstract: "USB" peripheral
Contextual Info: Features • • • • • • • USB V1.1 Compliant/12 Mbits per second Number and Size of Endpoints Fully Parametrizable in RTL Embedded Dual Port RAM for Endpoints Suspend/Resume Logic Ping-pong Mode 2 Memory Banks for Isochronous Endpoints Compatible With an Embedded ARM7TDMI Processor

ADM1068

Abstract: ADM1069 ADM1062 ADM1066 ADM1067
Contextual Info: AN-0997 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Ping-Pong Configuration Guide for ADM1062 to ADM1069 Devices by Naiqian Ren INTRODUCTION The ADM1062 to ADM1069 Super Sequencers are configurable supervisory/sequencing devices that offer a single-chip

"USB" peripheral

Contextual Info: Features • • • • • • • • USB V1.1-Compliant, 12 Mbits/s Number and Size of Endpoints Fully Parametrizable in RTL Embedded Dual-port RAM for Endpoints Suspend/Resume Logic Ping-pong Mode 2 Memory Banks for Isochronous Endpoints Compatible with Any 8-bit Microcontroller