PPO DATASHEET Search Results

X311

Abstract: 20-PIN EL1502 EL1502CM
Contextual Info: PRODUCT BRIEF I GNS DE S T W E ME N OR N ED F EPLACE nter at D N MME r t Ce ED R E C O M M E N D l S u ppo 1 R T O NO x31 nica REC Sheet Tech LANTEC October 12, 1999 NOData r u o act 1-888-E t n o c EL1502 FN7037 High Power Differential Line Driver/ Receiver

EL1501

Abstract: X311 EL1501CM
Contextual Info: PR ODUC T BRIEF NS E SI G D NT N EW FOR LACEME r at D E ente EN D R EP O M M E N D ED u ppo r t C C E R M S NOT RECOM chnical EC x311 e T O T Sheet March 1995, Rev. A N NData r A u act o 1-888-EL t n o c EL1501 FN7036 Differential Line Driver/Receiver Features

THL W8

Abstract: ICS98ULPA877A ICSSSTUAF32869A IDTCSPUA877A Q11A SSTU32864
Contextual Info: DATASHEET ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with

THL W8

Contextual Info: DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description IDT74SSTUBF32869A The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it

7120

Abstract: ICS98UAE877A IDT74SSTUAE32866A Q11A
Contextual Info: DATASHEET IDT74SSTUAE32866A 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation.

Contextual Info: DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL ICSSSTUAF32866B design of the ICSSSTUAF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32866B IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32869A IDTCSPUA877A Q11A SSTU32864
Contextual Info: DATASHEET ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with

DDR2 pin out

Abstract: 869A ICS98ULPA877A IDT74SSTUBF32869A IDTCSPUA877A Q11A SSTU32864
Contextual Info: DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description IDT74SSTUBF32869A The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it

ICS98ULPA877A

Abstract: IDT74SSTUBF32869A IDTCSPUA877A Q11A SSTU32864 IDT74SSTUBF
Contextual Info: DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description IDT74SSTUBF32869A The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it

Contextual Info: DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL I DT 7 4 SST U BF3 2 8 6 9 A The IDT74SSTUBF32869A includes a parity checking function. The IDT74SSTUBF32869A accepts a parity bit from the memory controller at its input pin PARIN one or

ICS98ULPA877A

Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
Contextual Info: DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL IDT74SSTUBF32866B design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

Contextual Info: DATASHEET IDT74SSTUAE32866A 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation.

ICS98ULPA877A

Abstract: ICSSSTUAF32866C IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32866B IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32866C IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

THL W8

Contextual Info: DATASHEET ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with

Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

Contextual Info: DATASHEET IDT74SSTUAE32866A 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation.

Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is

ICS98ULPA877A

Abstract: ICSSSTUAF32866C IDTCSPUA877A
Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is