PQ-20 14 PIN Search Results

Contextual Info: HYUNDAI H Y M 5 9 1 6 1 0 SEMICONDUCTOR 16M X S e r ie s 9-bit CMOS DRAM MODULE PRELIMINARY DESCRIPTION The HYM591610 is a 16M x 9-bit Fast page mode CMOS DRAM module consisting of nine HY5117100 in 24/28 pin SOJ or TSOF-II on a 30 pin glass-epoxy printed circuit board. 0.22pF decoupling capacitor is mounted for

Contextual Info: Ȋfl h y u h d a i 'f i SEMICONDUCTOR HYM59256A * 256KX 9-Bit CMOS DRAM MODULE M451201A-APR91 DESCRIPTION The HYM59256A is a 256K words by 9bits dynamic RAM module and consists o f Fast Page mode CMOS DRAMs of two HY534256J in 20/26 pin SOJ and one HY53C256LF in 18

Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020B – JUNE 1996 – REVISED SEPTEMBER 2001 D Military Operating Temperature Range: D D D D D D D D D D D D D D D D D ÉÉ ÉÉ 100 132 ÉÉ ÉÉ 1 99 33 67 ÉÉ ÉÉ 66 D ÉÉ ÉÉ ÉÉ ÉÉ 34 D D – 55°C to 125°C

Contextual Info: IS ISSI 61S 6432 64Kx 32 SYNCHRONOUS PIPELINE STATIC RAM PRELIMINARY JULY 1998 FEATURES DESCRIPTION • Internal self-timed write cycle T he IS 61S 64 32 is a h ig h -sp e e d , lo w -p o w e r synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium ,

Contextual Info: * 1-Cube PSX Family Data Sheet àÊL F eatures D e s c r ip t io n • SRAM -based, in-system programmable • Switch Matrix The PSX160, PSX128B and PSX96B are SRAM-based bus oriented switches with 160, 128 and 96 l/Os respectively. The devices are manufactured using a 0.6|jm CMOS process and

Intel overdrive

Contextual Info: in t e i Intel486 SX M ICROPROCESSOR IM PORTANT— Read This Section Before Reading The Rest Of The Data Sheet This data sheet describes the Intel486 SX microprocessor, the Intel OverDrive™ Processor, and the l n t e l 4 8 7 TM S X Math Coprocessor. All normal text describes the functionality for the Intel486 SX microproces­

Contextual Info: TMS320F240 DSP CONTROLLER SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002 D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D – Object Compatible With the TMS320C2xx – Source Code Compatible With TMS320C25 – Upwardly Compatible With TMS320C5x

Contextual Info: Intel 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: SM 73301 SM73301 RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT23-5 T ex a s In s t r u m e n t s Literature Number: SNOSB92A SM73301 Semiconductor RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT23-5 General Description Features

Contextual Info: LS201 ' * - I-Cube* 27 Port LAN Switching Element Description Features • Single chip, Fast Ethernet switching fabric • Up to 100 M bit per-port switching capacity • Supports 27 full duplex ports • Port trunking capability dynamic load balancing •

Contextual Info: A E M Ä N ] ! DMF©[^G!Mini K] in t e l 8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER Chip-select Unit — 6 Chip-select Pins — Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select — Programmable Wait States 0-15 for Each Chip Select

Contextual Info: [p [K ì@ y g T [F ^ E W Ö E W in te i 8-Mbit ( 5 1 2 K X 1 6 , 1 M X 8 SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY • Intel SmartVoltage Technology — 5V or 12V Program/Erase — 3.3V or 5V Read Operation — 60% Faster Typical Programming at 12V VPP

IAGMF

Abstract: IDS500
Contextual Info: & I-Cube PS48 Data Sheet Features Description • SRAM-based, In-system Programmable • Non-Blocking Switch Matrix - User Configurable D atapath W idth of 4, 8, or 16 bits - Identical and Predictable Delays • 48 I/O Ports - Individually Program m able as Input,

Contextual Info: intei M8259A PROGRAMMABLE INTERRUPT CONTROLLER Military 8086, 8088, 80186 Compatible MCS -85 Compatible Eight-Level Priority Controller Expandable to 64 Levels Programmable Interrupt Modes Individual Request Mask Capability Single + 5V Supply No Clocks

Contextual Info: 000 PWR-82331 and PWR-82333 ILC DATA DEVICE _ _ CORPORATION_ SMART POWER 3-PHASE MOTOR DRIVES FEATURES DESCRIPTION APPLICATIONS The PWR-82331 and PWR-82333 are 30A 3-phase motor drive hybrids. The PW R-82331 has a 200V rating and uses MOSFETs in the output stage while the

Contextual Info: MULTI-ISSUE 64-BIT MICROPROCESSOR Features 79RC5000 * Large, efficient on-chip caches 32KB Instruction Cache, 32KB Data Cache 2-set associative in each cach Virtually indexed and physically tagged to minimize cache flushes Write-back and write-through selectable on a per page

Contextual Info: 1 » i l l 1 IF V 1 F 1 1 U 1 ‘! S y P r • W 0 L HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V3569S F ea tu re s: ♦ True Dual-Ported memory cells which allow simultaneous access of the same memory location ♦ High-speed clock to data access

Contextual Info: IDT723612 CMOS SyncBiFlFO 64 X 36 X 2 In te g r a t e d D e v ic e T e c h n o lo g y , In c. • • • • • FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: LM 49450 LM49450 I2S Input, 2.5W/Channel, Low EMI, Stereo, Class D Audio Sub-System withGround Referenced Headphone Amplifier, 3D Enhancement, and Headphone Sense Texa s In s t r u m e n t s Literature Number: SNAS440C t i o n LM 49450 ló a l Sem iconductor

TMS320C2

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C − APRIL 1999 − REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D − Object Compatible With the TMS320C2xx Family − Source Code Compatible With

Contextual Info: LS120 Data Sheet I-Cube Quad-Port Ethernet Switch Interface Description Features Supports both 10 and 100 Mbit Ethernet, with Half Duplex and Full Duplex modes. Cut-through or Store-and-Forward switching, selectable on a per-port basis. Supports Half Duplex and Full Duplex Flow