PRESET Search Results

TC9303AN

Abstract: 6LW6 TC9303 tc9304f LCD12 TC9319F TC9301AN TC9309F
Contextual Info: Digital Tuning System DTS (1) System IC-LSI System No. Controller PLL prescaler DTS-9 A3 Operating Voltage Crystal Oscittation TC9301AN TC9172AP 4.5-5.5V 7.2MHz TC9303AN TC9227P 4.5-5.5V 7.2MHz Major Functions Receiving Band Preset Memory * Station Clock

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

SN74HC74

Contextual Info: SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS094A - DECEMBER 1982 - REVISED JANUARY 1996 Package Options Include Plastic Small-Outline D , Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

7476 ic specifications

Abstract: ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
Contextual Info: SN547G, SN54LS76A, SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR D EC EM BE R 1 9 8 3 -R E V IS E D M A R C H • Dependable Texas Instruments Quality and Reliability TO P V IE W ] *^16 : i k iclkC 15 H 1 Q 1 prëC 2 14 : i q 1clrC 3 13 DGND

TC74ACT109

Contextual Info: TOSHIBA TC74ACT109 Dual J-K Flip-Flop with Preset and Clear Features: • High Speed: fmax = 185MHz typ. at Vcc = 5V • Low Power Dissipation: lcc = 4|xA (max.) at Ta = 25°C • Compatible with T IL Outputs: V,L = 0.8V (max.) VlH=2V (min.) • Symmetrical Output Impedance:

Contextual Info: TOSHIBA TC7WH74FU TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC7WH74FU D-TYPE FLIP FLOP WITH PRESET AND CLEAR The TC7WH74FU is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent

SN741

Abstract: SN54176
Contextual Info: SN54176, SN54177, SN74176, SN74177 35-MHz PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES M A Y 1 9 7 1 - R E V IS E D M A R C H 1988 Reduced-Power Versions of SN54196, SN 54197, SN74196, and SN74197 50-MHz Counters S N 5 4 1 7 6 , S N 5 4 1 7 7 . . . J PACKAGE

74HC113

Abstract: D Flip Flops
Contextual Info: SN 54H C 113. SN 74H C 113 DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1 9 8 7 T O P V IEW L J 14 1C LK Ü Dependable Texas Instruments Quality and Reliability 1 K L 1J C ip r e h description

74as74

Contextual Info: SN74ALS74A, SN74AS74, SN54ALS74A, SN54AS74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2M 1, APRIL 1982 - REVISED SEPTEM BER 1987 Package Options Includa Plaatlc "Sm a ll OutHna" Package!, Ceramlc Chip Carrlara. and Standard Plattlc and Caramic 300-mll

Contextual Info: SN74LVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET JANUARY 1993 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted 1CCR [ 1 1D [ 2 CMOS) Submicron Process • 1CLK [ 3 Designed to Facilitate Incident Wave

SN74ALS74

Abstract: LS74 74AS74 54ALS74 SN74AS74
Contextual Info: TYPES SN54ALS74, SN54AS74, SN74ALS74, SN74AS74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET D2661, APRIL 1 98 2-R EV ISED DECEMBER 1983 Package Options Include Both Plastic and Ceram ic Chip Carriers in Addition to Plastic and Ceram ic DIPs

Contextual Info: INTEGRATED TOSHIBA T O S H IB A CM O S D IG IT A L IN TEG R A TED CIR C U IT CIRCUIT T E C H N IC A L TC74AC1 09P/F/FN DATA SILICO N M O N O LITH IC DUAL J - K FLIP FLOP WITH PRESET AND CLEAR The TC74AC109 is an advanced high speed CMOS DUAL JK FLIP FLOP fabricated with silicon gate and double - layer

ls74a

Abstract: 74as74
Contextual Info: SN 54ALS74A, SN 54AS74, SN 74ALS74A, SN 74 A S 74 DUAL D TYPE POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET D 2 6 6 1 , APRIL 1 9 8 2 - • SN 54A LS74A , S N 54A S 74 . . . J PACKAGE SN 74A LS74A , S N 74A S 74 . , . D OR N PACKAGE Package O ption s Include P lastic "S m a ll O u tlin e "

Contextual Info: TOSHIBA TC74ACT74P/F/FN/FT TO SHIBA CM OS D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74ACT74P, TC74ACT74F, TC74ACT74FN, TC74ACT74FT DUAL D -T Y P E FLIP FLOP WITH PRESET AND CLEAR The TC74ACT74 is an advanced high speed CMOS D - FLIP FLOP fabricated with silicon gate and double - layer metal

54HC112

Contextual Info: SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 02684, DECEMBER 1982-REVISED SEPTEMBER 1987 SN54HC112 . . . J PACKAGE SN74HC112 . . . D OR N PACKAGE TOP VIEW ] 1CLK C 1 O l 6 H V CC i k C 2 15 3 1CLR 14 H 2CLR u [ 3

74ls74a ic

Abstract: SN54L74
Contextual Info: TYPES SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, SN7474, SN74H74, SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR R E V IS E D D E C E M B E R 1983 Package Options Include Both Plástic and Ceram ic Chip Carriers in Addition to Plastic

Contextual Info: TOSHIBA TC74AC109 Dual J-K Flip-Flop with Preset and Clear Features: • High Speed: fmax = 200MHz typ. at Vcc = 5V • Low Power Dissipation: lcc = 4|iA (max.) at Ta = 25°C • High Noise Immunity: VNIH = VN1L = 28% Vcc (min.) • Symmetrical Output Impedance: ll0H>= Iol = 24mA

tl401

Contextual Info: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCAS046 - D2957. DECEMBER 1986 - REVISED APRIL 1993 54ACT11074. . . J PACKAGE 74ACT11074. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible

SN54ALS109

Contextual Info: TYPES SN54ALS109, SN54AS109, SN74ALS109, SN74AS109 DUAL J K POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 0 2 6 6 1 , A P R IL 1 9 8 2 — R E V IS E D D E C E M B E R 1 9 8 3 • Package Options Include Both Plastic and Ceramic SN 54A LS109. S N 54A S 109 • . . J PACKAGE

MH 7472

Abstract: ic 7472 ttl 7472 ttl TTL 7472
Contextual Info: SN5472, SN7472 AND-GATED J-K M ASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1963 - REVISED MARCH 1988 S N 5 4 7 2 . . J P AC KA G E S N 7 4 7 2 . . . N P AC K A G E Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages TO P VIE W

74ls112 function table

Contextual Info: TOSHIBA TC74HC112AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC112AP, TC74HC112AF, TC74HC112AFN Note The JEDEC SOP (FN) is not available in DUAL J - K FLIP-FLOP WITH PRESET AND CLEAR Japan The TC74HC112A is a high speed CMOS DUAL J - K FLIP

Contextual Info: 74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET _ SCAS064A - D3339. JUNE 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Fully Buffered to Offer Maximum Isolation

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE

Contextual Info: SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A- MARCH 1987 - REVISED OCTOBER 1993 • Package Options Include Plastic Smali-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs