R-S FLIP FLOP Search Results

ic D flip flop 7474

Abstract: T flip flop IC JK flip flop IC ic 7474 features of ic 7474 7474 j-k flip flop pin IC 7474 d flip flop 7474 7474 jk flip flop ic 7474 truth table
Contextual Info: INTEGRATED CIRCUITS TTL DUAL JK M A S T E R /S L A V E FLIP FLOP PIN CONNECTION GENERAL DESCRIPTION T O P VIEW The flip flops described herein are TTI, T ra ns is to r-T ra ns is to r Logic dual ]K Ma ster/Slave flip flops. A s y n c h r o r o u s CLEAR in p ut s are provided

74ls112 pin diagram

Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Contextual Info: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,

Contextual Info: F102311* F10631^ HIGH SPEED DUAL D FLIP-FLOP F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10231/F10631 contains two master/slave D-type flip-flops. The internal clock is the O R of two clock inputs, one common to both flip-flops. The O R clock permits the use of one input a s a clock pulse and the other a s an active LO W enable.

207d

Abstract: 63Q7
Contextual Info: SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR S D A S 2 0 7 D -A P R IL 1 9 8 2 - R EVISED MAY 1996 • ALS174 and AS174 Contain Six Flip-Flops With Single-Rail Outputs

F95231

Contextual Info: F95231 HIGH SPEED DUAL D FLIP-FLOP D E S C R IP T IO N — T h e F95 2 31 c o n ta in s tw o m a s te r /s la v e D ty p e flip -flo p s . T h e in te r ­ n a l c lo c k is th e OR of tw o c lo ck in p u ts , o n e c o m m o n to b o th flip - flo p s T h e OR c lo c k

Contextual Info: S E M IC O N D U C T O R 74LVX374 Low Voltage Octal D Flip-Flop w ith 3-STATE O utputs General Description Features The LVX374 is a high-speed, low -pow er octal D-type flip-flop featuring separate D-type inputs fo r each flip-flop and 3-STATE outputs fo r bus-oriented applications. A buffered

FJJ116

Abstract: 6472N 7472N 7472N equivalent FJJ111 J111A FJJ111A
Contextual Info: T.T.L. SIN G LE M A S T E R -S LA V E JK FLIP-FLOPS Fiji 11 Correspond to 74 Séries types 7472IM, 6472N FjjIIIA FJJII6 TENTATIVE DATA T h ese d evices a r e tr a n s is to r - tr a n s is to r logic m a s te r-s la v e JK flip-flops in the F J s e r ie s of in te g rate d c irc u its . Thë FJJ111 c o rre sp o n d s to '74

ZD302

Contextual Info: A I R C H I L D S E M IC G N D U C T Ü R Revised D ecem ber 1998 tm 74AC175 • 74ACT175 Quad D-Type Flip-Flop General Description Features The AC /AC T175 is a high-speed quad D-type flip-flop. The device is useful fo r general flip-flop requirem ents w here

74LS175PC

Abstract: 74175DC 74175 truth table 74175PC 74175 74LS175FC A7417 74ls175 pin diagram 74LS175DC 74S175P
Contextual Info: 175 C O N N E C T IO N D IA G R A M P IN O U T A 74175 //sW 74S175 ô / / s- v v 74LS175 à QUAD D FLIP-FLOP 1 ! S' ‘/ " S yjyu m ^ O D E S C R IP T IO N — Th e '175 is a N g h speed quad D flip-flop. Th e device is use­ ful fo r general flip -flo p requirem ents where c lo c k and cle ar Inputs are com ­

HCT273

Abstract: SN54HCT377 SN74HCT377
Contextual Info: SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE S C LS067B- NOVEMBER 1 9 8 8 - REVISED JUNE 1996 SN54HCT377 . . . J O R W PACKAGE SN74HCT377 . . . DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible C o ntain E ig h t Flip -F lo p s W ith S ingle-R ail

SN54AHCT174

Abstract: SN74AHCT174
Contextual Info: SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR S C L S 4 1 9 A -J U N E 1 9 9 8 - R EVISED S E P TE M B E R 1998 Inputs Are TTL-Voltage Compatible EP/C Enhanced-Performance Implanted CMOS Process Contain Six Flip-Flops With Single-Rail Outputs

HD10231

Contextual Info: H D 10231 High Speed Dual D -type M aster-Slave Flip Flops flip-flop. Asynchronous S e t S and R eset(R ) over­ low state. In this case, the enable inputs perform the function of controlling the common clock. ride C lock (C c ) and Clock Enable (C E ) inputs.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D-Type Flip-Flop with 3-S tate Output MC74VHC374 The MC74VHC374 is an advanced high speed CMOS octal flip -flip with 3 -sta te output fabricated with silicon gate CMOS technology. It achieves high speed operation sim ila r to e q u ivale n t B ipolar S chottky TTL w hile

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D-Type Flip-Flop with 3-S tate Output MC74VHC574 The MC74VHC574 is an advanced high speed CMOS octal flip -flip with 3 -sta te output fabricated with silicon gate CMOS technology. It achieves high speed operation sim ila r to e q u ivale n t B ipolar S chottky TTL w hile

7473N

Abstract: 6473N FJJ121 FJJ121A FJJ126
Contextual Info: T.T.L. DUAL MASTER-SLAVE JK FLIP-FLOPS FJJI2I F JJI2 IA Correspond to 74 Series types 7473N, 6473IM FJJI26 TENTATIVE DATA T hese devices a re tra n sisto r-tra n s is to r logic dual JK m aste r-sla v e flip flops in the F J se rie s of integrated circ u its. The FJJ121 corresponds to

Contextual Info: 74AC11374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS S C A S 214A - JU LY 1987 - R EVISED A P R IL 1996 • Eight D-Type Flip-Flops in a Single Package • 3-State Bus-Driving True Outputs • Full Parallel Access for Loading • Flow-Through Architecture Optimizes

7476N

Abstract: tir 101a 6476N FJJ191 FJJ191A FJJ196 16-mA TTL 7476N TO74 package
Contextual Info: T.T.L. D U A L M A ST E R -SLA V E JK FLIP-FLOPS W IT H PRESET A N D CLEAR F J II9 I Ell 101A C| 11QA Correspond to 74 Series types 7476N, 6476N ^ TENTATIVE DATA T h ese d evices a r e tr a n s is to r - tr a n s is to r logic dual JK m a s te r-s la v e flip flops, w ith p r e s e t and c le a r inputs, in the F J s e r ie s of in te g rate d c irc u its .

Contextual Info: June 1997 Dual J-K Flip-Flop with Set and Reset File Number 3773 Functional Diagram The CD54HC109F3A and CD54HCT109F3A are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock 1CP and 2CP . The flip-flop is set and reset by active-low S and R,

7474N

Abstract: FJJ131 FJJ131A FJJ136
Contextual Info: Fill31 FJJI3IA FJJI36 T.T.L. EDGE-TRIGGERED DUAL D-TYPE FLIP-FLOPS Correspond to 74 Series types 7474N, 6474M T ENTATIVE DATA T h ese d evices a r e tr a n s is to r - tr a n s is to r logic e d g e -trig g e re d dual D -type flip -flo p s, w ith d ire c t, c le a r and p r e s e t inputs and com plem entary Q and

cd40138

Abstract: cd4013b CD4013 H R C M F 3B 334
Contextual Info: w Tex a s In s t r u m e n t s CD4013B Types D ata sheet acquired from Harris Sem iconductor S C H S023 CMOS Dual ‘D*-Type Flip-Flop Features: • Set-Reset capability ■ Static flip-flop operation — retains state indefinitely with clock level either

Contextual Info: u n i i i i c o t o r l U / t r L O ^ / O t o c tal D -type P o s i ti v e - e d g e - tr ig g e r e d Flip-Flops with Clear The HD74LS273, positive-edge-triggered flip-flops utilize LS T T L circuitry to implement D-type flip-flo p logic w ith a direct

74ls171

Abstract: 4LS1
Contextual Info: TYPES SN54LS171, SN74LS171 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR R E V IS E D D E C E M B E R 1 9 8 3 • Contains Four Flip-Flops with Double Rail Outputs S N 5 4 L S 1 7 1 . . J O R W P A C K A G E S N 7 4 L S 1 7 1 . . D, J O R N P A C K A G E TOP VIEW

Contextual Info: 3.3V CMOS SINGLE POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOP IDT74ALVC1G79 D E S C R IP T IO N : FE A T U R E S : This single positive-edge-triggered D-type flip-flop is built using - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; advanced dual metal CMOS technology. The ALVC1G79 is designed

Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS534 Octal D-Type Flip-Flop With General Description The ’LS534 is a high speed, low pow er octal D -type flip-flop featuring separate D -type inputs for each flip-flop and 3-STATE outputs for bus oriented applications. A buffered