RDN 240/ 12 Search Results

XR68C681

Contextual Info: XR-88C681/68C681 CMOS Dual Channel UART DUART GENERAL DESCRIPTION FEATURES The EXAR Dual Univeral Asynchronous Receiver and Transmitter (DUART) is a data communications device that provides two fully independent full duplex asynchronous communications channels in a single

XR-88C861

Abstract: 88C681 68C681 88c681 features XR88C861 XR68C681
Contextual Info: XR-88C681/68C681 2 £ *E X A R CMOS Dual Channel UART DUART GENERAL DESCRIPTION FEATURES The EXAR Dual Univeral Asynchronous Receiver and Transmitter (DUART) is a data communications device that provides two fully independent full duplex asynchronous communications channels in a single

rdn 100

Abstract: SCN26562 SCN26562C4A52 SCN26562C4N48
Contextual Info: Philips Semiconductors Product specification Dual universal serial communications controller DUSCC SCN26562 • Parity and FCS (frame check sequence LRC or CRC) generation DESCRIPTION The Philips Semiconductors SCN26562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI

SCN26562

Abstract: SCN26562C4A52 SCN26562C4N48
Contextual Info: INTEGRATED CIRCUITS SCN26562 Dual universal serial communications controller DUSCC Product specification 1995 May 1 IC19 Philips Semiconductors PHILIPS PHILIPS 711DflSb ôbT Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC)

SERCON410B

Abstract: SERCON816 8501 xd SERCOS Reference Manual RDN 240/ 12 SERCON410B equivalent PQFP100 SERC816 TDA 1410 pt 915
Contextual Info: SERCON816 SERCOS INTERFACE CONTROLLER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single-chip controller for SERCOS interface Real time communication for industrial control systems 8/16-bit bus interface, Intel and Motorola control signals Dual port RAM with 2048 word *16-bit

SERCON816

Abstract: SERCON410 SERCOS Reference Manual
Contextual Info: SERCON816 SERCOS INTERFACE CONTROLLER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single-chip controller for SERCOS interface Real time communication for industrial control systems 8/16-bit bus interface, Intel and Motorola control signals Dual port RAM with 2048 word *16-bit

SD00203

Abstract: SCN26562C4A52 cen 30 SCN26562 SCN26562C4N48
Contextual Info: INTEGRATED CIRCUITS SCN26562 Dual universal serial communications controller DUSCC Product specification IC19 Data Handbook Philips Semiconductors 1995 May 01 Philips Semiconductors Product specification Dual universal serial communications controller (DUSCC)

receiver philips fr 310

Abstract: RIA 250
Contextual Info: Philips Semiconductors Data Communications Products Product specification Dual universal serial communications controller DUSCC DESCRIPTION SCN26562 • Parity and FCS (fram e check sequence LR C or CRC) generation The Philips Sem iconductors SC N26562 Dual Universal Serial

W98M6

Abstract: XR88C681MN-S0969 09WF0 part marking MICROCIRCUIT RDN 240/ 12 W98M681 XR88C681MN 88011 EXAR MARKING CODE Radiation Assured Devices
Contextual Info: 1. SCOPE 1.1 Scope. This drawing describes a commercially available microcircuit with radiation tolerance. 1.1.1 *RTA* This drawing contains a radiation tolerance assured item and/or processes. All changes to items or processes and all proposed substitutions of items identified as RTA on the drawing, must be evaluated and

N25R

Abstract: SCN26562 ls 7456
Contextual Info: Philips Components-Signetics Docum ent No. 8 5 3 -0 3 0 7 ECN No. 94624 Date of Issue O ctober 30, 1990 Status P roduct Specification SCN26562 Dual universal serial communications controller DUSCC Data Com m unication Products DESCRIPTION PIN DESCRIPTIONS

transistor 7k cen

Contextual Info: NAPC/ SIGNETICS Signetics SIE D • bbSHiHH 0 3551=10 S C N 26542 ô r -*-*/ Dual Multiprotocol Serial Controller (DMSC M ic ro p ro c e s s o r Division DESCRIPTION The Signetics SCN26542 Dual Multi­ protocol Serial Controller (DMSC) is a single-chip MOS-LSI communications de­

intel 8255

Abstract: 8255 pin diagram intel 8255 pin diagram 8255 a pin diagram 8255 programmable peripheral interface 8255 pin configuration 8255 input output in all mode 8255 8255 input output port CFI2550B
Contextual Info: CFI2550B CFI2550B 8255 GENERAL DESCRIPTION: INTEL 8255 PROGRAMMABLE PERIPHERAL INTERFACE CFI2550B is compatible with Intel 8255. It is also compatible in I/Os except for the fact that each bidirec­ tional data bus is separated into two signals. However, the user can make it fully compatible with 8255 by

25 MHZ TXC

Abstract: 37A6 SCN26542C2A52 SCN26542C2N40 gg552 CRC generator and checker
Contextual Info: NAPC/ SIGNETICS Signetics SIE D I ^ 53^34 G O S S n a a • T '-r? S * - 3 7 - o 7 SC N26542 Dual Multiprotocol Serial Controller DMSC Microprocessor Division D ES C R IPTIO N The Signetics SCN26542 Dual Multi­ protocol Serial Controller (DMSC) Is a single-chip MOS-LSI communications de­

280/ana 6180

Abstract: 240/ANA 6180 R/ana 6180 equivalent HA 2800 vm618
Contextual Info: VM 6180 Series » VValue TC Inc. the Customer 970801 FEATURES • General - Designed for Use With Four-Terminal MR Heads - 3-Line Serial Interface with Readback Provides Programmable Bias Current, Write Current, Head Selection, Thermal Asperity, and Servo Operation

hr6p

Abstract: CN1718 VM61210 100 LMR 40
Contextual Info: w VM 61210 W 10-CHANNEL, MAGNETO-RESISTIVE HEAD, READ/WRITE PREAMPLIFIER WITH SERVO WRITE FEATURES • High Performance - Read Voltage Gain = 150 V/V Typical - Input Noise = 0.70 nV/'/Hz Typical - Head Inductance Range = 100 nH to 500 nH - Write Current Range = 2 0 - 4 0 mA

TRANSISTOR SMD MARKING CODE 1P3

Abstract: 68C681 88C681 D5071 D-10 TCS0102 TRANSISTOR AO SMD MARKING DS2429 WN smd transistor B/TRANSISTOR SMD MARKING CODE 1P3
Contextual Info: DISTRIBUTION STATEMENT A . Approved for public release; distribution is unlimited. 1. SCOPE 1.1 Scope. This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices".

DS638PP1

Abstract: EP9315 EP9315 UART2 EP9315-CBZ AC97 ARM920T EP9315-CB EP9315-IB MO-151
Contextual Info: EP9315 Data Sheet FEATURES • • • • • Linux , Microsoft® Windows® CE enabled MMU 100 MHz System Bus • • • • MaverickCrunch Math Engine • Floating point, integer and signal processing instructions • Optimized for digital music compression and

VM612

Abstract: 22iJ RDN 1W hard disk head preamp
Contextual Info: V M 6122 2-CHANNEL, MAGNETO-RESISTIVE HEAD, READ/WRITE PREAMPLIFIER WITH SERVO WRITE August, 1997 FEATURES • High Performance - Read Voltage Gain = 150 or 350 V/V Typical

Contextual Info: TS-S07D130B July, 2008 10Gb/s XFP Optical Transceiver Module SXP3100NV SR-1/I-64.1, 10GBASE-LR/LW, 1200-SM-LL-L, 1310nm DFB, PIN-PD, RoHS-6 Features ‹ 10Gb/s Serial Optical Interface ¾ High quality and reliability optical device and sub-assemblies ¾ 1310nm DFB laser for up to 10km operation

graphical LCD screen 20 pin with sound ic

Abstract: 61A8 AC97 ARM920T EP9312 EP9312-CB MO-151 audio sender wireless das2 internet radio
Contextual Info: EP9312 Data Sheet FEATURES • • • • • Universal Platform Systemon-Chip Processor 200 MHz ARM920T Processor • 16 Kbyte Instruction Cache • 16 Kbyte Data Cache Linux , Microsoft® Windows® CE enabled MMU 100 MHz System Bus • • • MaverickCrunch Math Engine

EP9312

Abstract: EP9312-CB EP9312-CBZ MO-151 AC97 ARM920T CS8952 audio sender wireless ac97 with microcontroller EP9312 jukebox
Contextual Info: Revision 1.10 EP9312 Revision D Data Sheet FEATURES • • • • • Linux , Microsoft® Windows® CE enabled MMU 100 MHz System Bus • • • MaverickCrunch Math Engine • Floating point, integer and signal processing instructions • Optimized for digital music compression and

AC97

Abstract: ARM920T CS8952 EP9312 EP9312-CB EP9312-CBZ MO-151 audio sender wireless AH1T EP9312 jukebox
Contextual Info: Revision 1.00 EP9312 Revision D Data Sheet FEATURES • • • • • Linux , Microsoft® Windows® CE enabled MMU 100 MHz System Bus • • • MaverickCrunch Math Engine • Floating point, integer and signal processing instructions • Optimized for digital music compression and

atapi standards

Abstract: EP9315 EP9315-CBZ PCMCIA SRAM Card 61A8 AC97 ARM920T EP9315-CB MO-151 audio sender wireless
Contextual Info: EP9315 Data Sheet FEATURES • • • • • Linux , Microsoft® Windows® CE enabled MMU 100 MHz System Bus • • • • MaverickCrunch Math Engine • Floating point, integer and signal processing instructions • Optimized for digital music compression and

ISS55

Contextual Info: VM 61210 » VTC In c . Value the Customer 10-CHANNEL, MAGNETO-RESISTIVE HEAD, READ/WRITE PREAMPLIFIER WITH SERVO WRITE 960801 FEATURES • High Performance - Read Voltage Gain = 150 V/V Typical - Input Noise = 0.70 nV/VHz Typical - Head Inductance Range = 100 nH to 500 nH