Untitled
Abstract: No abstract text available
Text: ALUMINUM ELECTROLYTIC CAPACITORS RXC Series: Low Impedance, High Temperature FEATURES 105°C, 2000 ~ 3000 hours assured Low ESR, suitable for switching power supplies, UPS For ballast use, 3000 ~ 5000 hours assured Smaller size with large permissible ripple current
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120Hz,
120Hz)
120Hz
100KHz
C1CD02
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SiI151BCT100
Abstract: SiI151A MS-026-AED-HD MS-026-AED PanelLink
Text: Technology SiI 151B PanelLink Receiver Data Sheet Document # SiI-DS-0051-C SiI 151B PanelLink Receiver Data Sheet Silicon Image, Inc. SiI-DS-0051-C September 2002 Application Information To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon
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SiI-DS-0051-C
SiI151BCT100
SiI151BCTG100
100-pin
MS-026AED
SiI151A
MS-026-AED-HD
MS-026-AED
PanelLink
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rxied1
Abstract: RXIED Z16C32 AD10 AD11 AD12 AD14 SL1660 rxc 151
Text: PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION 1 Z16C32 SL1660 ONLY 1 IUSC INTEGRATED UNIVERSAL SERIAL CONTROLLER GENERAL DESCRIPTION The IUSC Integrated Universal Serial Controller is a single-channel multple protocol data communications device with on-chip dual-channel DMA. The integration of a highspeed serial communications channel with a high performance DMA facilitates higher data throughput than is possible with discrete serial/DMA chip combinations. The buffer chaining capabilities combined with features like
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Z16C32
SL1660
CP97HHS0100
rxied1
RXIED
AD10
AD11
AD12
AD14
rxc 151
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SiI151ACT100
Abstract: JEDEC Package Code MS-026-AED PanelLink AN0007 SiI151A PanelLink Transmitter
Text: SiI 151A PanelLink Receiver Datasheet May 2000 Features The SiI 151A receiver uses PanelLink Digital technology to support high resolution displays up to SXGA. The SiI 151A receiver supports up to true color panels 24 bit/pixel, 16.7M colors in 1 or 2 pixels/clock mode. In
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SiI151ACT100
SiI/DS-0029-A
1-888-PanelLink
JEDEC Package Code MS-026-AED
PanelLink
AN0007
SiI151A
PanelLink Transmitter
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7495 shift register
Abstract: DNCM00
Text: Advance Data Sheet August 1996 DNCM00 10 Mbit/s Ethernet MAC ASIC Macrocell Features • 10 Mbit/s Ethernet MAC designed to operate with industry-standard physical layer transceivers ■ Operation in half- or full-duplex environment ■ Asynchronous reset with no clocks present
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DNCM00
DNCM00
DS95-217ASIC
7495 shift register
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JEDEC Package Code MS-026-AED
Abstract: AN0007 DVI FIBER SiI151ACT100 panel link silicon image qo-10
Text: SiI 151A PanelLink Receiver Datasheet July 2000 Features The SiI 151A receiver uses PanelLink Digital technology to support high resolution displays up to SXGA. The SiI 151A receiver supports up to true color panels 24 bit/pixel, 16.7M colors in 1 or 2 pixels/clock mode. In
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SiI151ACT100
SiI/DS-0029-B
1-888-PanelLink
JEDEC Package Code MS-026-AED
AN0007
DVI FIBER
panel link silicon image
qo-10
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SiI151ACT100
Abstract: JEDEC Package Code MS-026-AED PanelLink AN0007 PanelLink Transmitter SII151 SILICON IMAGE APPLICATION NOTES Mapping* silicon image AN-0007 SiI-DS-0029-C
Text: SiI 151A PanelLink Receiver Datasheet March 2001 Features The SiI 151A receiver uses PanelLink Digital technology to support high resolution displays up to SXGA. The SiI 151A receiver supports up to true color panels 24 bit/pixel, 16.7M colors in 1 or 2 pixels/clock mode. In
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SiI151ACT100
SiI-DS-0029-C
1-888-PanelLink
JEDEC Package Code MS-026-AED
PanelLink
AN0007
PanelLink Transmitter
SII151
SILICON IMAGE APPLICATION NOTES
Mapping* silicon image AN-0007
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Untitled
Abstract: No abstract text available
Text: Approval sheet Capacitor Arrays Series MULTILAYER CERAMIC CAPACITORS Automotive Capacitor Arrays Series MY Qualified to AEC-Q200 4 x 0402 NP0 & X7R Dielectrics *Contents in this sheet are subject to change without prior notice. Page 1 of 19 ASC_ Automotive Cap Array_(MY)_026B_AS
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AEC-Q200
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Untitled
Abstract: No abstract text available
Text: LTC1344A Software-Selectable Cable Terminator U DESCRIPTION FEATURES • ■ The LTC 1344A featur es six softw ar e- selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 V.11 100Ω minimum differential load, V.35 T-network load or an open circuit for use
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LTC1344A
RS422
RS232
RS423
LTC1543
LTC1544,
LTC1344A
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Untitled
Abstract: No abstract text available
Text: LTC1344 Software-Selectable Cable Terminator FEATURES • U ■ DESCRIPTIO The LTC 1344 features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 V.11 100Ω minimum differential load, V.35 T-network load or an open circuit for use
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LTC1344
RS422
RS232
RS423
LTC1343,
LTC1344
RS485
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EIA530
Abstract: EIA530-A LTC1343 LTC1344 RS423 RS449 b1344 rxc 151
Text: LTC1344 Software-Selectable Cable Terminator U DESCRIPTION FEATURES • ■ The LTC 1344 features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 V.10 100Ω minimum differential load, V.35 T-network load or an open circuit for use
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LTC1344
RS422
RS232
RS423
LTC1343,
LTC1344
RS485
EIA530
EIA530-A
LTC1343
RS423
RS449
b1344
rxc 151
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EIA530
Abstract: LTC1344 LTC1344A LTC1543 LTC1544 RS423 RS449 V11 interface
Text: Final Electrical Specifications LTC1344A Software-Selectable Cable Terminator February 1998 U DESCRIPTION FEATURES • ■ The LTC 1344A features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 V.11 100Ω minimum differential load, V.35 T-network load or an open circuit for use
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LTC1344A
RS422
RS232
RS423
LTC1543
LTC1544,
LTC1344A
EIA530
LTC1344
LTC1544
RS423
RS449
V11 interface
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DB15 dwg
Abstract: CRC-16 DB01 DB03 SCN2653
Text: Philips Semiconductors Product specification Multi-protocol communications controller MPCC DESCRIPTION SCN2652/SCN68652 FEATURES • DC to 2Mbps data rate • Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC • Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
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SCN2652/SCN68652
SCN2652/68652
16-bit
SCN2652
SD00075
SCN2652/SCN2653
DB15 dwg
CRC-16
DB01
DB03
SCN2653
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CR43-5R6
Abstract: RXD TXD DTR DSR RS232 EIA530 EIA530-A LTC2844 LTC2844CG LTC2846 RS449 DTE X21 LTC28441
Text: Final Electrical Specifications LTC2844 3.3V Software-Selectable Multiprotocol Transceiver April 2002 U DESCRIPTIO FEATURES • ■ ■ The LTC 2844 is a 4-driver/4-receiver multiprotocol transceiver. The LTC2844 and LTC2846 form the core of a complete software-selectable DTE or DCE interface port that
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LTC2844
LTC2844
LTC2846
RS232,
RS449,
EIA530,
EIA530-A,
LTC2846.
28-lead
CR43-5R6
RXD TXD DTR DSR RS232
EIA530
EIA530-A
LTC2844CG
RS449
DTE X21
LTC28441
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SiI151CT100
Abstract: Mapping* silicon image AN-0007 AN-0007-A AN-0008-A AN-0005 an0008a SILICON IMAGE APPLICATION NOTES PanelLink analog pixel driver SII151CT
Text: SiI 151 PanelLink Digital Receiver July 1999 General Description Features The SiI151 uses PanelLink Digital technology to support displays ranging from VGA to SXGA 25-112 MHz which is ideal for desktop and specialty applications. The SiI151 receiver supports up to true color panels (24 bit/pixel,
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SiI151
SiI151CT100
/DS-0007-E
Mapping* silicon image AN-0007
AN-0007-A
AN-0008-A
AN-0005
an0008a
SILICON IMAGE APPLICATION NOTES
PanelLink
analog pixel driver
SII151CT
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ic cd 4060 pin diagram
Abstract: mdio level translator st 42 valor DP83924A dura12 aui rj45 DP83924AVCE d1514 rxdt-2-5 40T8
Text: October 1997 DP83924A Quad 10 Mb/s Ethernet Transceiver General Description Features The Quad 10 Mb/s Ethernet Transceiver is a 4-Port Encoder/Decoder ENDEC that includes all the circuitry required to interface four Ethernet Media Access Controllers (MACs) to 10BASE-T. This device is ideally suited for
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DP83924A
10BASE-T.
10BASE-T
select-180-530
ic cd 4060 pin diagram
mdio level translator
st 42 valor
dura12
aui rj45
DP83924AVCE
d1514
rxdt-2-5
40T8
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Ultra Small_01R5_AS
Abstract: No abstract text available
Text: Approval sheet Ultra Small Series 01R5 MULTILAYER CERAMIC CAPACITORS Ultra-small Series (6.3V to 16V) 01005 Size NP0, X7R & X5R Dielectrics RoHS Compliance *Contents in this sheet are subject to change without prior notice. Page 1 of 8 ASC_ Ultra Small_(01R5)_026C_AS
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manchester decoder
Abstract: rxc 151 T7210APC T7210A
Text: AT&T Advance Data Sheet T7210A Manchester Decoder and Interface Chip MDIC Features Compatible with IEEE 802.3 10BASE-T proposed standards Recovers data and clock signals from Incoming 10 Mbits/s Manchester data Contains precision timing elements controlled by a
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T7210A
10BASE-T
T7300
D-8043
3-02A/04
DS89-098SMOS
manchester decoder
rxc 151
T7210APC
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Untitled
Abstract: No abstract text available
Text: IPfôlKLIMIMfôV in y 82501 ETHERNET SERIAL INTERFACE Compatible with IEEE 802.3, Ethernet and Cheapernet Specifications Driving/Receiving IEEE 802.3 Transceiver Cable 10-Mbps Operation Fail-Safe Defeatable Watchdog Timer Circuit to Prevent Continuous Transmissions
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10-Mbps
10-MHz
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Untitled
Abstract: No abstract text available
Text: DATA SHEET DRAFT DISTINCTIVE CHARACTERISTICS Supports High-speed Source Routing or Source Routing Transparent Bridging for up to eight ports Glue-free operation with the MUSIC MU9C1480 LANCAM and Ti or LANGuys formerly C&T Token Ring chip sets • Automatically selects Source Routed or Transparent
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MU9C1480
MU9C8148s
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Z16C32
Abstract: No abstract text available
Text: P r e l im in a r y C u s t o m e r P r o c u r e m e n t S p e c if ic a t io n Z16C32 SL1660 O nly . TM IU S C In t e g r a t e d U n iv e r s a l S e r ia l C o n t r o l l e r GENERAL DESCRIPTION The IUSC Integrated Universal Serial Controller is a sin
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Z16C32
SL1660
MIL-STD-883C
80-Lead
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82501
Abstract: 82c502 82586 generation circuit of manchester 0-12V 198S txc 20MHz
Text: PfölKLOßflOIMISIV inteT 82501 ETHERNET SERIAL INTERFACE Compatible with IEEE 802.3, Ethernet and Cheapernet Specifications Driving/Receiving IEEE 802.3 Transceiver Cable 10-Mbps Operation Fail-Safe Defeatable Watchdog Timer Circuit to Prevent Continuous
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10-Mbps
10-MHz
82501
82c502
82586
generation circuit of manchester
0-12V
198S
txc 20MHz
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T7213
Abstract: T7213EC Traffic Light Controller Circuit Block Diagram 104 j 50 nis d LTE Receiver manchester code encoder diagram state m-tron mtron crystal oscillator T7213-EC NIS capacitors
Text: Data Sheet November 1991 L âA T & T Microelectronics T7213 Dual Interface Station Chip Features Description • Compatible with IEEE 802.3 standards for Attachm ent Unit Interface AUI ■ Compatible with IEEE 802.3 10BASE-T draft standards for Twisted-Pair (TP) Interface
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T7213
10BASE-T
DS91-202SMOS
DS90-125SMOS)
T7213EC
Traffic Light Controller Circuit Block Diagram
104 j 50 nis d
LTE Receiver
manchester code encoder diagram state
m-tron
mtron crystal oscillator
T7213-EC
NIS capacitors
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uas 111
Abstract: AD10 AD11 AD12 AD14 DC3012 Z16C35
Text: — C'iARCOM D C 3 0 1 2 DOCUMENT CONTROL— .IAS TER C u s t o m e r Pr o c u r e m e n t S p e c if ic a tio n < £ Z iI ß Ö Z16C35 CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER GENERAL DESCRIPTION The Z16C35ISCC is a CMOS superintegrated device with
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DC3012
Z16C35ISCC
uas 111
AD10
AD11
AD12
AD14
Z16C35
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