S-PQFP-G100 PACKAGE POWERPAD LAYOUT Search Results

S-PQFP-G100 PACKAGE POWERPAD LAYOUT Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
TPH9R00CQH		Toshiba Electronic Devices & Storage Corporation	MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N)
TPH9R00CQ5		Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 150 V, 64 A, 0.009 Ω@10 V, High-speed diode, SOP Advance / SOP Advance(N)
TPH1R306PL		Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 60 V, 100 A, 0.00134 Ω@10 V, SOP Advance / SOP Advance(N)
TPHR8504PL		Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 40 V, 150 A, 0.00085 Ω@10 V, SOP Advance / SOP Advance(N)
TPHR7404PU		Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 40 V, 0.00074 Ω@10V, SOP Advance, U-MOSⅨ-H

S-PQFP-G100 PACKAGE POWERPAD LAYOUT Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
100-PIN Abstract: TFP101 TFP101A TFP101APZP TFP101PZP Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119C - MARCH 2000 − REVISED OCTOBER 2003 D Supports XGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1	Original	TFP101, TFP101A SLDS119C TFP101A 100-PIN TFP101 TFP101APZP TFP101PZP	PDF
Contextual Info: TFP101, TFP101A TI PanelBus DIGITAL RECEIVER SLDS119C - MARCH 2000 − REVISED OCTOBER 2003 D Supports XGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 86 MHz Digital Visual Interface (DVI) Specification Compliant1	Original	TFP101, TFP101A SLDS119C	PDF
DVI dual link receiver Abstract: DVI dual link transmitter CIRCUIT DIAGRAM OF 9 INCH TFT MONITOR dvi dual link schematic S-PQFP-G100 Package footprint DDC Panel dvi 24 pin diagram RX-2 -G s S-PQFP-G100 Package powerPAD land pattern TFP503 Contextual Info: TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 D Supports UXGA Resolution Output Pixel D D D D D D Reduced Power Consumption From 1.8-V Rates up to 165 MHz Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection (HDCP) Specification Compliant1	Original	TFP503 SLDS149 48-Bit DVI dual link receiver DVI dual link transmitter CIRCUIT DIAGRAM OF 9 INCH TFT MONITOR dvi dual link schematic S-PQFP-G100 Package footprint DDC Panel dvi 24 pin diagram RX-2 -G s S-PQFP-G100 Package powerPAD land pattern TFP503	PDF
S-PQFP-G100 Package example land pattern Contextual Info: TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 D Supports UXGA Resolution Output Pixel D D D D D D Reduced Power Consumption From 1.8-V Rates up to 165 MHz Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection (HDCP) Specification Compliant1	Original	TFP503 SLDS149 48-Bit S-PQFP-G100 Package example land pattern	PDF