sr flip flop
Abstract: DN74LS113 MA161
Text: DN74LS113 LS TTL DN74LS Series D N 7 4 L S 1 1 3 ^ 7 ^ U S 3 Dual J-K Negative Edge-Triggered F lip -F lo p s with Set) • Description P-l D N74LS113 contains tw o negative-edge triggered J-K flip flop circuits, each w ith independent clock-CP, J, K, and
|
OCR Scan
|
PDF
|
DN74LS
DN74LS113
DN74LS113
14-pin
S0-140)
MA161.
trS15ns,
sr flip flop
MA161
|
Untitled
Abstract: No abstract text available
Text: I LS TTL DN74LS Series DN74LS113 DN74LS113 Dual J-K Negative Edge-Triggered Flip-Flops with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.
|
OCR Scan
|
PDF
|
DN74LS
DN74LS113
DN74LS113
14-pin
SO-14D)
MA161.
S15ns,
|
Untitled
Abstract: No abstract text available
Text: Signetics 54161, 54163, 54LS161 A, 54LS163A Counters 4-Bit Binary Counters Military Logic Products FEATURES • Synchronous counting and loading • Two Count Enable inputs for n-blt cascading • Positive edge-triggered clock • Asynchronous reset ’161
|
OCR Scan
|
PDF
|
54LS161
54LS163A
54LS163A)
54LSXXX
500ns
S15ns
54XXX
400S2
|
98915
Abstract: No abstract text available
Text: Signetics I 54LS86, 54S86 Gates Quad TWo-lnput Excluslve-OR Gates Military Logic Products H FUNCTION TABLE INPUTS Product Specification ORDERING INFORMATION ORDER CODE DESCRIPTION OUTPUT 54LS86/BCA, 54S86/BCA A B Y 14-Pin Ceramic DIP L L H H L H L H L H H
|
OCR Scan
|
PDF
|
54LS86,
54S86
54LS86/BCA,
54S86/BCA
14-Pin
54LS86/BDA,
54S86/BDA
54LS86/B2A,
54S86/B2A
98915
|
Untitled
Abstract: No abstract text available
Text: PAN ASONIC IND L/ELEK -CIC3- 75 Ï F | bTBEñSa D007SSM 3 6 932 852 PANASONIC IND L *ELECTRONIC 72C 0 7 2 5 4 LS TTL DN74LS^U-X D DN74LS377/DN74LS377S DN74LS377/DN74LS377S Octal Positive Edge-Triggered D-Type Flip-Flops with Enable D N 7 4 L S 3 7 7 /S IÍ, è - » * ® « 7 0 7 ? *>' J c íM
|
OCR Scan
|
PDF
|
D007SSM
DN74LS
DN74LS377/DN74LS377S
S15ns,
|
Untitled
Abstract: No abstract text available
Text: PANASONIC INDL/ELEK -CIO 72 • - - . . ■ , T È I h13SñS2 GDD7025 □ 1 ~ JH _ _ 693285 2 PANASONIC INOL t E L ECTRONIC 72C LS TTL DN74LSS/U-X 07Q25 B D N 74LSÌ 26A/D N 74LS126AS DN74LS126A/DN74LS126AS Quad Bus Buffer Gates with 3-state Outputs
|
OCR Scan
|
PDF
|
GDD7025
07Q25
DN74LS126A/DN74LS126AS
DN74LSS/U-X
74LS126AS
14-DIP
S0-14D
hT32flS2
DDQ7027
DN74LS'
|
54LS195
Abstract: No abstract text available
Text: Signetics 54LS195A Shift Register 4-Bit Parallel Access Shift Register Product Specification Military Logic Products appears as four common clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs D0 - D3 is transferred to
|
OCR Scan
|
PDF
|
54LS195A
54LS195A
54LSXXX
500ns
s15ns
1N3064,
54LS195
|
DN74LS170
Abstract: T13V
Text: LS TTL DN74LS Series DN74LS170 DN74LS170 io ¡70 4 - b y - 4 R egister F ile s with Open C ollector Outputs • Description P -2 D N 7 4 L S 1 7 0 is a 4 -w o r d b y 4 -b it re g ister file w it h o p e n c o lle c t o r o u tp u ts . ■ Features • In d e p e n d e n t read a d d r ess a n d w r ite a d d r ess fo r s im u l
|
OCR Scan
|
PDF
|
DN74LS
DN74LS170
DN74LS170
16-pin
SO-16D)
T13V
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS161A DN74LS161A lu f c Synchronous 4 -bit Binary Counters • Description P-2 DN 74LS161A is a settable synchronous 4-bit binary hexa decim al co u n ter w ith direct-coupled reset input. ■ Features • Direct coupled reset input and synchronous set input
|
OCR Scan
|
PDF
|
DN74LS
DN74LS161A
74LS161A
32MHz
16-pin
SO-16D)
|
DN74LS153
Abstract: M74LS
Text: LS TTL DN74LS Series DN74LS153 DN74LS153 M74.LS. 155 Dual 4 - l i n e to 1 - lin e Data S e le c t o r s / Multiplexers • Description P-2 DN74LS153 contains tw o 4-line to 1-line data selector/ m ultiplexer circuits. ■ Features • • • • Independent enable input for each circuit
|
OCR Scan
|
PDF
|
DN74LS
DN74LS153
DN74LS153
16-pin
SO-16D)
trS15ns,
M74LS
|
LR9 panasonic
Abstract: No abstract text available
Text: PANASONIC INDL/ELEK ÍIC } 7E Í É | 1^32052 693285.2 PANASONIC INDL tE LE CT RON IC L S T T L DDD7111 _ 3 W~ 7 2C 07 111 oT’W ’ H '•fi; DN74LS1 81 /DN74LS1 81S D N 7 4 L S 5 > ' J - X DN74LS181 DN74LS181S 4 - b it A rith m etic Logic Unit /F u n c t io n G enerator
|
OCR Scan
|
PDF
|
DDD7111
DN74LS1
/DN74LS1
DN74LS181
DN74LS181S
LR9 panasonic
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS160A DN74LS160A 74LSUo à Synchronous Decade Counters • Description P -2 D N 7 4 L S 1 6 0 A is a settable synchronous decade counter w ith direct-coupled reset input. ■ Features • D irect-cou pled reset input and synchronous set input
|
OCR Scan
|
PDF
|
DN74LS160A
74LSUo
DN74LS
DN74LS160A
16-pin
ISO-16D)
S15ns,
|
54S138
Abstract: 54ls138 TE307
Text: Signetics 54LS138, 54S138 Decoders/Demultiplexers l-of-8 Decoder/Demultiplexer Product Specification Military Logic Products FEATURES E, E2 and one active High (E3). Every output will be High unless E, and E 2 are Low and E3 is High. This multiple enable
|
OCR Scan
|
PDF
|
54LS138,
54S138
1-of-32
54LSXXX
54SXXX
500ns
500ns
s15ns
54S138
54ls138
TE307
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS114 DN74LS114 ivj'7q_ uSiiq- Dual J-K Negative Edge-Triggered F lip-F lops with Set,Common Reset and Common Clock • Description P-1 D N 74L S 1I4 contains tw o negative-edge triggered J-K flipflop circuits w ith com m on clock-CP and direct-coupled reset
|
OCR Scan
|
PDF
|
DN74LS
DN74LS114
|
|
|
Untitled
Abstract: No abstract text available
Text: DN74LS160A LS TTL DN74LS Series D N 7 4 L S 1 6 A Synchronous Decade Counters • Description P -2 DN 74LS160A is a settable synchronous decade counter w ith direct-coupled reset input. ■ Features • • • • D irect-coupled reset in p u t and synchronous set input
|
OCR Scan
|
PDF
|
DN74LS160A
DN74LS
74LS160A
16-pin
500kH
S15ns,
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS163A DN74LS163A 74^163 A Synchronous 4 -bit Binary Counters • Description P-2 DN 74LS163A is a settable synchronous 4-bit binary hexa decim al counter w ith synchronous reset input. ■ Features • • • • Synchronous reset and set inputs
|
OCR Scan
|
PDF
|
DN74LS
DN74LS163A
DN74LS163A
74LS163A
16-pin
500kH
S15ns,
|
074LS
Abstract: DN74LS393 LS293 LS93 MA161
Text: LS TTL DN74LS Series DN74LS393 DN74LS393 J0 7 4 LS 3R3 Dual 4 - b i t Binary Counters • D escription P-1 DN 74LS393 con tain s tw o asynchronous 4-bit binary hexa decim al co u n ter circuits w ith direct-coupled reset inputs. ■ Features • • •
|
OCR Scan
|
PDF
|
DN74LS
DN74LS393
074LS
DN74LS393
LS293
35MHz
14-pin
MA161
LS93
|
DN74LS163A
Abstract: MA161 D20ns
Text: LS TTL DN74LS Series D N 7 4 L 1 S 6 3 DN74LS163A 7 A LS 4 / 6 3 A Synchronous 4 -bit Binary Counters • Description P-2 DN 74LS163A is a settable synchronous 4-bit binary hexa decim al counter w ith synchronous reset input. ■ F eatu res • • •
|
OCR Scan
|
PDF
|
DN74LS
DN74LS163A
DN74LS163A
16-pin
SO-16D)
MA161
D20ns
|
DN74LS364
Abstract: DN74LS364S
Text: PANASONIC 69 3 2 8 f 2 INDL/ELEK PANAS ON IC -CICÏ 7E » Ë J bTBEflSE 0[][]7a30 □ IN OL * E L E C T R O N IC 72C 07230 LS TTL DN74LSS/U-X . DN74LS364/DN74LS364S “ ö ~ 7 - C b5~ DN 74LS364/ DN74LS364S Octal Positive Edge-Triggerd D-Type Flip-Flops with 3 - s ta te Outputs
|
OCR Scan
|
PDF
|
69328f2
DN74LS
DN74LS364/DN74LS364S
DN74LS364
DN74LS364S
DN74LS364/StÂ
400mV
20-DIP
SO-20D
DN74LS^
DN74LS364S
|
DN74LS136
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS136 DN74LS1 36 Kj Iq. L S Quad 2 - input Exclusive OR Gates with Open Collector Outputs) P-1 • Description DN74LS136 contains four 2-input exclusive OR gate circuits with open collector outputs. ■ Features • • • •
|
OCR Scan
|
PDF
|
DN74LS
DN74LS1
DN74LS136
14-pin
SO-14D)
trS15ns,
|
Untitled
Abstract: No abstract text available
Text: 54193, 54LS193 Signetics Counters Presettable 4-Bit Binary Up/Down Counters Military Logic Products Product Specification FEATURES • Synchronous reversible 4-bit binary counting • Asynchronous parallel load • Asynchronous reset clear • Expandable without external logic
|
OCR Scan
|
PDF
|
54LS193
54LS193
54XXX
500ns
1N916
1N3064,
54F193
|
Untitled
Abstract: No abstract text available
Text: 54LS377 Signetics Flip-Flop Octal D Flip-Flop With Clock Enable Product Specification Military Logic Products ORDERING INFORMATION FEATURES DESCRIPTION • Ideal for addressable register applications The 54LS377 has eight edge-triggered, D-type flip-flops with individual D inputs
|
OCR Scan
|
PDF
|
54LS377
54LS377
20-pln
54LSXXX
500ns
S15ns
1N916
1N3064,
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series D N 7 4 LS1 1 2 DN74LS112 i0 7 ^ IS ¡ ¡ ^ Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset H Description P -2 DN 74LS112 contains two negative-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and
|
OCR Scan
|
PDF
|
DN74LS
DN74LS112
74LS112
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS114 DN74LS114 Dual J-K Negative Edge-Triggered F lip-F lops with Set, Common Reset and Common Clock • Description DN74LS114 contains two negative-edge triggered J-K flipflop circuits with common clock-CP and direct-coupled reset
|
OCR Scan
|
PDF
|
DN74LS
DN74LS114
DN74LS114
|
