SA8R Search Results

Contextual Info: SIEMENS High Performance 32-Bit RISC Microprocessor SAB-R2000A In c lu d in g o n -c h ip m e m o r y m a n a g e m e n t a n d c a c h e c o n tro l w ith s u p p o r t fo r u p to t h r e e e x te r n a l c o p ro c e s s o rs in c lu d in g t h e S A B -R 2 0 1 0 A flo a tin g p o in t a c c e le r a to r .

M915

Contextual Info: /T T * li. S G S -IH O M S O N lÄ G M IIL i » « © ! S T LC 5 4 3 2 2Mbit C E P T & PRIM ARY RATE CONTROLLER DEVICE PR ELIM IN A R Y DATA • ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER CEPT STANDARD ■ ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2)

mips r2000a

Abstract: R2000A SAB-R2020 R2010 mips processor SAB-R2000
Contextual Info: SIEM ENS High Performance Floating-Point Coprocessor SAB-R2010A based on Advanced RISC Architecture with four Independent Arithmetic Functional Units Advance Inform ation • Fully conform s to ANSI/IEEE standard 754-1985 for Binary floating-point Arithm etic

CLCC84

Abstract: SAB-R2000 R2000A MIPS FPA Siemens R2000 SAB-R2000A SAB-R2010A SAB-R2010A-12-QJ CLCC 84 R2010 mips processor
Contextual Info: SIEMENS High Performance Floating-Point Coprocessor SAB-R2010A Based on advanced RISC architecture with four independent arithmetic functional units Advance Information • Fully conforms to ANSI/IEEE standard 754-1985 for binary floating-point arithmetic

pj 98 ak

Abstract: m915 5v SAM3X intel 915 M915 FORI200 PQFP44 STLC5432 STLC5432Q TT 46 N 16 LOF
Contextual Info: n rz S C S -T H O M S O N ^ 7#. R!flD ^ lllLll©lM©liülD g§ STLC5432 2Mbit C EPT & PRIM ARY RATE CONTROLLER DEVICE PRODUCT PREVIEW • ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER (CEPT STANDARD . ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2)

VAC 4097

Abstract: M915 FOR120 STLC5432 STLC5432Q TQFP44 D1529
Contextual Info: STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE PRELIMINARY DATA July 1996 ORDERING NUMBER: STLC5432Q VCCA CS LO1 LO2 DPI P0 LI1 VT LI2 P1 GNDA PIN CONNECTION Top view 44 43 42 41 40 39 38 37 36 35 34 GNDD 1 33 BXDI SA/RESET 2 32 AL0 DIN 3 31 AL1 A/D0

Contextual Info: SIEMENS High Performance Floating-Point Coprocessor SAB-R2010A Based on advanced RISC architecture with four independent arithmetic functional units A dvance Inform ation • Fully conform s to ANSI/IEEE standard 754-1985 for binary floating-point arithmetic

TT 46 N 16 LOF

Abstract: VAC 4097 s-av71
Contextual Info: /= T S G S -T H O M S O N STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE P R ELIM IN A R Y DATA • ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER CEPT STANDARD ■ ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2) ■ HDB3/BIN ENCODER AND DECODER ON

SAM3X

Contextual Info: S G S -1 H 0 M S 0 N > STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE PRODUCT PREVIEW • ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER CEPT STANDARD . ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2) ■ HDB3/BIN ENCODER AND DECODER ON

VAC 4097

Abstract: L4097-X004 M915 4097x012 SGV01 l4097 FOR120 STLC5432 STLC5432Q TQFP44
Contextual Info: STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE PRELIMINARY DATA July 1996 ORDERING NUMBER: STLC5432Q VCCA CS LO1 LO2 DPI P0 LI1 VT LI2 P1 GNDA PIN CONNECTION Top view 44 43 42 41 40 39 38 37 36 35 34 GNDD 1 33 BXDI SA/RESET 2 32 AL0 DIN 3 31 AL1 A/D0

yb4 bridge diode

Abstract: national timer switch tb 179 Y81-Y8F CFC5 g1 rc16 EZOM SIEMENS BST t TB17 JT-G703 JT-G704
Contextual Info: MT9071 Quad T1/E1/J1 Transceiver Preliminary Information Features • • • • • • • • • DS5430 4 T1/E1/J1 framers and longhaul/shorthaul LIUs LIU sensitivity is 36dB in T1 and 40dB in E1 Internal reference switching PLL with holdover capability