SCBD002B Search Results

A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

Contextual Info: SN74CBT3386 10-BIT BUS-EXCHANGE SWITCH WITH EXTENDED VOLTAGE RANGE SCDS022 - MAY 1995 DB, DW, OR PW PACKAGE TOP VIEW BE [ 1 U [ 2 [ 3 [ 4 [ 5 [ 6 [ 7 [ 8 [ 9 [ 10 [ 11 VDD [ 12 1B1 1A1 1A2 1B2 2B1 2A1 2A2 2B2 3B1 3A1 description The SN74CBT3386 provides ten bits of

Contextual Info: SCDS002C - NOVEMBER 1992 - REVISED MAY 1995 DB, DW, OR PW PACKAGE TOP VIEW Functionally Equivalent to QS3245 Standard '245-Type Pinout 5-iî Switch Connection Between Two Ports NC [ 1 A1 [ 2 TTL-Compatible Control Input Levels A2 [ 3 A3 [ 4 A4 [ 5 Package Options Include Shrink

Contextual Info: SN74CBT3257 QUADRUPLE 2-BIT TO 1-BIT FET MULTIPLEXER/DEMULTIPLEXER SCDS017-MAY 1995 I • • • • S[ 1 1B1 [ 2 1B2 [ 3 1A [ 4 description The SN74CBT3257 is a quadruple 2-bit to 1-bit high-speed TTL-compatible FET multiplexer/ demultiplexer. The low on-state resistance of the

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCAS279B-JANUARY 1993 - REVISED JULY 1995 I • EP/C Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MII-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74LVC157 QUADRUPLE 2-LINE TO 1-UNE DATA SELECTOR/MULTIPLEXER SCAS292B-JANUARY 19 9 3 - REVISED JULY 1995 I • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model

Contextual Info: CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS _ SCAS335A-DECEMBER 1992-R E V IS E D NOVEMBER 1995 D PACKAGE TOP VIEW Low Output Skew for Clock-Distribution and Clock-Generatlon Applications

Contextual Info: SN74LVC827 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS306B - MARCH 1993 - REVISED JULY 1996 • EPIC Enhanced-Performance Implanted CMOS Submicron Process db , dw , o r pw packaqe (t o p v ie w ) Typical Vqlp (Output Ground Bounce) < 0.8 V at Vcc = 3-3 V, TA = 25'C

Contextual Info: SN74LVC863 9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS31OA - M A RCH 1993 - REVISED JULY 1996 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C | DB, DW, OR PW PACKAQE

SN74LVC162244

Contextual Info: SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS I SCAS546 - OCTOBER 1995 10Ê 1Y1 1Y2 GND 1Y3 1Y4 Output Ports Have Equivalent 26-Q Series Resistors, So No External Resistors Are Required Typical V q l p Output Ground Bounce < 0.8 V at Vc c = 3.3 V, TA = 25°C

Contextual Info: SN74LVCU04 HEX INVERTER SCAS282B - JANUARY 1993 - REVISED JULY 1995 D, DB, OR PW PACKAGE TOP VIEW • EP/C (Enhanced-Performance Implanted CMOS) Submicron Process I • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model

D2B4

Abstract: H1B13
Contextual Info: SN54ABT32543, SN74ABT32543 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS230B - JUNE 1992 - REVISED JULY 1994 • Members of the Texas Instruments Wldebus+ Family • State-of-the-Art EPIC-llB™ BICMOS Design Significantly Reduces Power Dissipation

Contextual Info: SN74LVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 3CES081A - DECEMBER 1 9 95 - REVISED JANUARY 1998 DQQ OR DL PACKAOE TOP VIEW Member of the Texas Instruments Wldebus Family EP/C™ (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce)

Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442C – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC

Contextual Info: SN54ABT374, SN74ABT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS111D – FEBRUARY 1991 – REVISED JULY 1994 • • • • State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA

Contextual Info: www.ti.com SN74LVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS FEATURES • • • • • • • Member of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce)

Contextual Info: SN74LVC112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET _ SCAS28BA-JANUARY 1 9 9 3 - REVISED JULY 1995 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC544 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS I SCAS346A - MARCH 1994 - REVISED JULY 1995 DB, DW, OR PW PACKAGE TOP VIEW Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C LEB A[ 1 U [ 2 A1[ 3 A2 [ 4 A3[ 5 A4[ 6 A5 [ 7

LVT573

Abstract: SN54LVT573 SN74LVT573 SN74LVT573DBLE SN74LVT573DBR SN74LVT573DW
Contextual Info: SN54LVT573, SN74LVT573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS138D − MAY 1992 − REVISED JULY 1995 D D D D D D 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE SN54LVT573 . . . FK PACKAGE TOP VIEW

8C12

Abstract: 8EN10 LVT16543 SN54LVT16543 SN74LVT16543
Contextual Info: SN54LVT16543, SN74LVT16543 3.3ĆV ABT 16ĆBIT REGISTERED TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SCBS148C − MAY 1992 − REVISED JULY 1995 D State-of-the-Art Advanced BiCMOS D D D D D D D D D D D SN54LVT16543 . . . WD PACKAGE SN74LVT16543 . . . DGG OR DL PACKAGE

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

CDC337

Abstract: CDC337DBLE CDC337DW CDC337DWG4 CDC337DWR CDC337DWRG4 CDC337NS MS-013
Contextual Info: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs

PC MOTHERBOARD CIRCUIT diagram

Abstract: CDC9841 ALL MOTHERBOARD CIRCUIT DIAGRAM CLK12
Contextual Info: CDC9841 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS SCAS458D – DECEMBER 1994 – REVISED APRIL 1996 D D D D D D D D D D D Four CPU Clock Outputs With Programmable Frequency 50 MHz, 60 MHz, and 66 MHz Six Clock Outputs at Half-CPU Frequency