SCLS Search Results

SN74HC74

Contextual Info: SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS094A - DECEMBER 1982 - REVISED JANUARY 1996 Package Options Include Plastic Small-Outline D , Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO

Contextual Info: SN54HC367, SN74HC367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS _ SCLS309A - JANUARY 1996 - REVISED JULY 1996 High-Current 3-State Outputs Drive Bus Lines, Buffer Memory Address Registers, or Drive up to 15 LSTTL Loads True Outputs SN54HC367

Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS174A - MARCH 1984 - REVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible SN54HCT240. . . J OR W PACKAGE SN74HCT240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer

SN54HCT240

Abstract: 8S63
Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS _ SCLS174A - MARCH 1984 - REVISED JANUARY 1996 • Inputs Are TTL-Voltage Compatible • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • SN54HCT240 . . . J OR W PACKAGE

Contextual Info: SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069S- NOVEMBER 198« - REVISED MARCH 1996 • ■ I • • Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers I I •

Contextual Info: SN54AHCU04, SN74AHCU04 HEX INVERTERS SCLS234A - OCTOBER 1995 - REVISED MARCH 1996 SN54AHCU04 . . . J OR W PACKAGE SN74AHCU04. . . D, DB, N OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V V^c EPIC (Enhanced-Performance Implanted CMOS) Process Unbuffered Outputs

74HC269

Contextual Info: SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES SCLS134A - DECEMBER 1982 - REVISED JANUARY 1996 8-Blt Parallel-Out Storage Register Performs Serlal-to-Parallel Conversion With Storage Asynchronous Parallel Clear Active-High Decoder Enable Input Simplifies Expansion

Contextual Info: SN54HC623, SN74HC623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS149A - DECEMBER 1982 - REVISED JANUARY 1996 Lock Bus-Latch Capability True Logic High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options include Plastic Small-Outline DW and Ceramic Flat

Contextual Info: SN54HC7002, SN74HC7002 QUADRUPLE POSITIVE-NOR GATES WITH SCHMITT-TRIGGER INPUTS _ SCLS033B - MARCH 1984 - REVISED JULY 1996 • Operation From Very Slow Input Transitions SN54HC7002 . . . J OR W PACKAGE SN74HC7002. . . D OR N PACKAGE TOP VIEW

Contextual Info: SN54HCT646, SN74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS _ SCLS178A-MARCH 1984- HEVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths

Contextual Info: SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS009A-MARCH 1 9 8 4 - REVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible SN54HCT373 . . . J OR W PACKAGE SN74HCT373. . . DW OR N PACKAGE TOP VIEW Eight High-Current Latches In a Single

Contextual Info: SN54HC253, SN74HC253 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS _ SCLS133A-DECEMBER 1982 - REVISED JANUARY 1996 3-State Version of 'HC153 High-Current Inverting Outputs Drive up to 15 LSTTL Loads

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES _ SCLSQ76A - DE CE M B E R 1982 - REVISED JA NUARY 1996 • Package Options Include Plastic Small-Outllne D , Shrink Small-Outllne (DB), Thin Shrink Small-Outllne (PW), and Ceramic Flat (W) Packages, Ceramic Chip

SCLS11

Contextual Info: SN54HC151, SN74HC151 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SCLS11 OB-DECEMBER 1982 - JULY 1996 8-Line to 1-Llne Multiplexers Can Perform as: - Boolean Function Generators - Parallel-to-Serlal Converters - Data Source Selectors Package Options Include Plastic

Contextual Info: SN54LV574, SN74LV574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS1 O flB - MARCH 1993 - REVISED APRIL 1996 • • • • • • EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vcc. TA = 25°C

Contextual Info: SN54HC688, SN74HC688 8-BIT IDENTITY COMPARATORS SCLS01OA - OECEMBER 1982 - REVISED JANUARY 1996 • • Compare Two 8-Blt Words Package Options Include Plastic Small-Outllne DW and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and

Contextual Info: SN54AHCT00, SN74AHCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS229F – OCTOBER 1995 – REVISED OCTOBER 1998 D D D SN54AHCT00 . . . J OR W PACKAGE SN74AHCT00 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AHCT374, SN74AHCT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS241H – OCTOBER 1995 – REVISED OCTOBER 1998 D D D Inputs Are TTL-Voltage Compatible EPIC  Enhanced-Performance Implanted CMOS Process Latch-Up Performance Exceeds 250 mA Per

Contextual Info: SN54AHCT374, SN74AHCT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS241I – OCTOBER 1995 – REVISED NOVEMBER 1999 D D D D EPIC  Enhanced-Performance Implanted CMOS Process Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per

Contextual Info: SN54HC374, SN74HC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS141C – DECEMBER 1982 – REVISED JULY 1998 D D D D SN54HC374 . . . J OR W PACKAGE SN74HC374 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Eight D-Type Flip-Flops in a Single Package

SNJ54HC373FK

Contextual Info: SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B – DECEMBER 1982 – REVISED MAY 1997 D D D D Eight High-Current Latches in a Single Package High-Current 3-State True Outputs Can Drive up to 15 LSTTL Loads Full Parallel Access for Loading

Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255E – DECEMBER 1995 – REVISED NOVEMBER 1998 D D D SN54AHC74 . . . J OR W PACKAGE SN74AHC74 . . . D, DB, DGV, N, OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V VCC

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS076B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC02 . . . J OR W PACKAGE SN74HC02 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline