SDRAM Search Results

Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590 – DECEMBER 1997 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps

ASPEN

Contextual Info: ASPEN Express Device Multi-PHY CellBus Access Device TXC-05806 PRODUCT INFORMATION APPLICATIONS • • • • • ATM Access Multiplexers DSLAM Applications Remote Access Equipment ATM LAN Switch Frame Relay Switch Connection Table SDRAM 15 Row/Col

Contextual Info: 240PIN DDR2 667 Unbuffered DIMM 1GB With 64Mx8 CL5 TS128MLQ64V6J Description Placement The TS128MLQ64V6J is a 128M x 64bits DDR2-667 Unbuffered DIMM. The TS128MLQ64V6J consists of 16pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin

Contextual Info: 240PIN DDR2 533 Registered DIMM 1024MB With 64Mx8 CL4 TS128MQR72V5J Placement Description The TS128MQR72V5J is a 128M x 72bits DDR2-533 Registered DIMM. The TS128MQR72V5J consists of 18 pcs 64Mx8 bits DDR2 SDRAMs in 60 ball FBGA package, 2 pcs register in 96 ball uBGA package, 1 pcs

Contextual Info: 200PIN DDR2 400 SO-DIMM 256MB With 32Mx16 CL3 TS32MSQ64V4M Description Placement The TS32MSQ64V4M is a 32M x 64bits DDR2-400 SO-DIMM. The TS32MSQ64V4M consists of 4pcs 32Mx16its DDR2 SDRAMs in 84 ball FBGA packages and a 2048 bits serial EEPROM on a 200-pin printed

Contextual Info: 214PIN DDR2 533 Micro-DIMM 256MB With 32Mx16 CL4 TS32MMQ64V5M Description Placement The TS32MMQ64V5M is a 32M x 64bits DDR2-533 J Micro-DIMM. The TS32MMQ64V5M consists of 4pcs 32Mx16bits DDR2 SDRAMs in 84 ball FBGA packages and a 2048 bits serial EEPROM on printed circuit board

Contextual Info: 240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Description Placement The TS64MLQ64V8J is a 64M x 64bits DDR2-800 Unbuffered DIMM. The TS64MLQ64V8J consists of 8 pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin printed

Contextual Info: 184PIN DDR333 Unbuffered DIMM 1024MB With 64Mx8 CL2.5 TS128MLD64V3J Description Placement The TS128MLD64V3J is a 64Mx64bits Double Data Rate SDRAM high-density Module for DDR333. The TS128MLD64V3J consists of 16pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil

Contextual Info: 240PIN DDR2 800 Unbuffered DIMM 1GB With 64Mx8 CL5 TS128MLQ64V8J Description Placement The TS128MLQ64V8J is a 128M x 64bits DDR2-800 Unbuffered DIMM. The TS128MLQ64V8J consists of 16pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin

PC133 registered reference design

Contextual Info: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

IS43DR81280B

Abstract: IS46DR16640B IS43DR16640B-25DBL IS46DR16640B-3DBLA IS43DR16640B IS43DR16640B-3DBL
Contextual Info: IS43/46DR81280B/L, IS43/46DR16640B/L PRELMINARY INFORMATION AUGUST 2012 1Gb x8, x16 DDR2 SDRAM FEATURES •               Clock frequency up to 400MHz 8 internal banks for concurrent operation

CMS3216LAF

Abstract: CMS3216LAG CMS3216LAH
Contextual Info: CMS3216LAx-75xx 32M 2Mx16 Low Power SDRAM Revision 0.2 January, 2007 Rev0.2, Jan. 2007 CMS3216LAx-75xx Document Title 32M(2Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Mar.3rd, 2005 Preliminary 0.1 Add H(Pb-Free & Halogen Free) descriptions

Contextual Info: CMS4A16LAx–75Ex 128M 8Mx16 Low Power SDRAM Revision 0.5 May. 2007 Rev. 0.5, May. ‘07 CMS4A16LAx–75Ex Document Title 128M(8Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark Preliminary 0.0 Initial Draft Apr.25th, 2005 0.1

W9825G6JH

Abstract: A-04 w9825g6jh-6l w9825g6jh-6
Contextual Info: W9825G6JH 4 M  4 BANKS  16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION . 3 2. FEATURES . 3

74605

Contextual Info: AVED MEMORY PRODUCTS Where Quality & Memory Merge AVED16P664LS49-C75 16M X 64 SDRAM DIMM based on 16M X 8, 4 Banks, 4K REFRESH, 3.3V Synchronous DRAMs WITH SPD DESCRIPTION AVED Memory Products AVED16P664LS49-C75 is a 16M bit X 64 Synchronous Dynamic RAM high density memory module. The AVED Memory Products AVED16P664LS49-C75

Contextual Info: AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP366P1723AT2-C1H 16M X 64 SDRAM DIMM based on 16M X 8, 4 Banks, 4K REFRESH, 3.3V Synchronous DRAMs WITH SPD DESCRIPTION AVED Memory Products AMP366P1723AT2-C1H is a 16M bit X 64 Synchronous Dynamic RAM high density memory module. The AVED Memory Products AMP366P1723AT2-C1H

Contextual Info: AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP366P1623BTE-C75/H 16M X 64 SDRAM DIMM, Unbuffered, based on 8M X 8, 4 Banks, 4K Refresh, 3.3V Synchronous DRAMs WITH SPD DESCRIPTION AVED Memory Products AMP366P1623BTE-C75/H is a 16M bit X 64 Synchronous Dynamic RAM high density memory

Contextual Info: AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP374P1723AT2-C1L 16M X 72 SDRAM DIMM with ECC based on 16M X 8, 4 Banks, 4K REFRESH, 3.3V Synchronous DRAMs WITH SPD DESCRIPTION AVED Memory Products AMP374P1723AT2-C1L is a 16M bit X 72 Synchronous Dynamic

AVED8P664LS48-C75

Contextual Info: AVED MEMORY PRODUCTS Where Quality & Memory Merge AVED8P664LS48-C75 8M X 64 SDRAM SODIMM based on 4M X 16, 4 Banks, 4K Refresh, 3.3V Synchronous DRAMS with SPD DESCRIPTION AVED Memory Products AVED8P664LS48-C75 is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The

Contextual Info: AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP366P1723BT2-C75 16M X 64 SDRAM DIMM based on 16M X 8, 4 Banks, 4K REFRESH, 3.3V Synchronous DRAMs WITH SPD DESCRIPTION AVED Memory Products AMP366P1723BT2-C75 is a 16M bit X 64 Synchronous Dynamic RAM high density memory module. The AVED Memory Products AMP366P1723BT2-C75

Contextual Info: Preliminary Datasheet 1.5A DDR TERMINATION REGULATOR AP2301 General Description Features The AP2301 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 1.5A current continuously, offers enough

Contextual Info: AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP374P3323CT2-C75 32M X 72 SDRAM DIMM with ECC based on 16M X 8, 4 Banks, 4K REFRESH, 3.3V Synchronous DRAMs WITH SPD DESCRIPTION AVED Memory Products AMP374P3323CT2-C75 is a 32M bit X 72 Synchronous Dynamic

PCM-3362Z2-1GS6A1E

Abstract: PCM-3362 intel ICH 8 1960045487T001 pata i2c 1700003491 165313222B pin diagram of Dual core cpu PC 104 CPU 5P20
Contextual Info: PCM-3362 Intel Atom N450 PC/104-Plus SBC, CRT, LVDS, Ethernet, USB, COM, SATA, Onboard Flash Features I2C/SMbus ƒƒ Intel® Atom™ N450 1.66 GHz Processor and DDR2 667MHz SDRAM up to 2 GB RS-422/485 Power in Gigabit Ethernet ƒƒ Supports extended temperature -40 ~ 85° C

W9425G6JH

Contextual Info: W9425G6JH 4 M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4