SDRAM U221 Search Results

Contextual Info: PCS2I2310ANZ Product Preview 3.3 V SDRAM Buffer for Mobile PCS with 4 SO-DIMMs http://onsemi.com Description The PCS2I2310ANZ is a 3.3 V buffer designed to distribute high−speed clocks in mobile PC applications. The part has 10 outputs, 8 of which can be used to drive up to four SDRAM SO−DIMMs, and

Hitachi DSA00171

Contextual Info: HM5212165 シリ−ズ HM5212805 シリ−ズ 128M LVTTL interface SDRAM 66 MHz 2-Mword x 16-bit × 4-bank/4-Mword × 8-bit × 4-bank ADJ-203-289A Z ’98. 7.1 Rev. 1.0 概要 HM5212165 シリーズは，2097152 ワード × 16 ビット × 4 バンク構成の SDRAM です。HM5212805 シリー

DDR400B

Abstract: E1202
Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232ACBH 4M words x 32 bits Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: 144-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 2.5V −0.125V/+0.2V

48-PIN

Abstract: CDC318A
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

ADSP-TS201S

Abstract: AD1854 AD1871 ADDS-TS201S-EZLITE
Contextual Info: ADSP-TS201S EZ-KIT Lite Evaluation Kit for the TigerSHARC Processor Key Features • Dual ADSP-TS201S TigerSHARC Processors  • 4 MB 512k  8-bit flash memory • 32 MB (4M  64-bit) SDRAM • AD1871, stereo audio, 24-bit, 96 kHz, multibit, ∑–∆ ADC

DDR400B

Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232ACBH 4M words x 32 bits Specifications Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: 144-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 2.5V −0.125V/+0.2V

Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

ADSP-TS201S

Abstract: AD1871 ADSP-TS201S EZ-KIT Lite Evaluation Kit AD1854 ADDS-TS201S-EZLITE tigersharc in audio system tigersharc
Contextual Info: ADSP-TS201S EZ-KIT Lite Evaluation Kit for the TigerSHARC Processor Key Features • Dual ADSP-TS201S TigerSHARC Processors • 4 MB 512K ϫ 8-bit FLASH memory • 32 MB (4M ϫ 64-bit) SDRAM • AD1871, stereo audio, 24-bit, 96 kHz, multi-bit, ∑–∆ ADC

Contextual Info: CDC2510B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PC133 registered reference design

Abstract: CDC2509
Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

Contextual Info: CDC2509B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible

Contextual Info: CDC2510B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible

Contextual Info: CDC2509B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible

PC133 registered reference design

Abstract: CDC2509
Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PC133 registered reference design

Contextual Info: CDCVF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS637C − DECEMBER 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

N5208

Abstract: A114 A115 JESD22 JESD78 NCP5208 NCP5208DR2
Contextual Info: NCP5208 DDR−I/II Termination Regulator The NCP5208 is a linear regulator specifically designed for the active termination of DDR−I/II SDRAM. The device can be operated from a single supply voltage as low as 1.7 V. For DDR−I applications, the device is capable of sourcing and sinking current up

CDC2510B

Abstract: CDC2510BPWR CDCVF2510A CLY 70
Contextual Info: CDC2510B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PC133 registered reference design

Contextual Info: CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

PC133 registered reference design

Contextual Info: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9