SERIES 1810 MANUAL Search Results

SMLF13WBDW

Contextual Info: Data Sheet SMLF1 Series 1810（0704） 1.8x1.0mm （t=0.35mm） Features Color Type ・Thin, side-view package WB Specifications Absolute Maximum Ratings Ta＝25℃ Electrical and Optical Characteristics (Ta＝25℃) Emitting Power Chip Forward Voltage VF Reverse Current IR Chromaticity Coordinates Luminous Intensity IV

GRM155R60J105KE19D

Contextual Info: Application Note 1810 Author: Rahman Sobhan Evaluation Hardware/Software User Manual for ALS and Proximity Sensors Introduction Evaluation Package Online Order The Optical Sensor Evaluation Kit (OSEK) is designed to evaluate the performance of various Optical Sensor devices. This

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

Contextual Info: INDUSTRIAL FLOOR SCALES STANDARD SIZE DESIGN Free Factory Calibration when ordered with MDS41-S Benchtop Meter $720 . See Section D for complete details on the MDS41-S Shown smaller than actual size with MDS41-E benchtop meter, $720. See Section D for full

Contextual Info: MC10E163, MC100E163 5V ECL 2-Bit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 − A7, B0 − B7) is propagated to the output.

MC100E171

Abstract: MC10E171 MC10E171FN
Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E151

Abstract: MC10E151 MC10E151FN
Contextual Info: MC10E151, MC100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous

MC100E150

Abstract: MC10E150 MC10E150FN
Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

E112

Abstract: E212 MC100E112 MC10E112 E212 transistor
Contextual Info: MC10E112, MC100E112 5V ECL Quad Driver Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

MC100E101

Abstract: MC10E101 MC10E101FN MC10E101FNG
Contextual Info: MC10E101, MC100E101 5V ECL Quad 4-Input OR/NOR Gate Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. http://onsemi.com Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: •

MC100E166

Abstract: MC10E166 MC10E166FN
Contextual Info: MC10E166, MC100E166 5V ECL 9-Bit Magnitude Comparator Description The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation.

MC100E155

Abstract: MC10E155 MC10E155FN
Contextual Info: MC10E155, MC100E155 5V ECL 6−Bit 2:1 Mux−Latch Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

MC100E156

Abstract: MC10E156 MC10E156FN
Contextual Info: MC10E156, MC100E156 5V ECL 3-Bit 4:1 Mux-Latch Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is

tag 725

Abstract: MC100E104 MC10E104 MC10E104FN ECL IC NAND
Contextual Info: MC10E104, MC100E104 5V ECL Quint 2-Input AND/NAND Gate Description The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

MC100E150

Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

Contextual Info: MC10E122, MC100E122 5V ECL 9-Bit Buffer Description The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. http://onsemi.com Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

MC100E122

Abstract: MC10E122 MC10E122FN MC10E122FNG
Contextual Info: MC10E122, MC100E122 5V ECL 9-Bit Buffer Description The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. http://onsemi.com Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

MC100E150

Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

mr 4020

Abstract: mr 4030 MC100E150 MC10E150 MC10E150FN ul 1950
Contextual Info: MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

MC100E163

Abstract: MC10E163 MC10E163FN
Contextual Info: MC10E163, MC100E163 5V ECL 2-Bit 8:1 Multiplexer Description The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 − A7, B0 − B7) is propagated to the output.

Marking D1c

Abstract: MC100E101 MC10E101 MC10E101FN MC10E101FNG
Contextual Info: MC10E101, MC100E101 5V ECL Quad 4-Input OR/NOR Gate Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. http://onsemi.com Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: •

SOCKET PLCC28 layout

Abstract: MC100E164 MC10E164 MC10E164FN PLCC28 layout
Contextual Info: MC10E164, MC100E164 5V ECL 16:1 Multiplexer Description The MC10E/100E164 is a 16:1 multiplexer with a differential output. The select inputs SEL0, 1, 2, 3 control which one of the sixteen data inputs (A0 − A15) is propagated to the output. Special attention to the design layout results in a typical skew

Contextual Info: MC10E107, MC100E107 5V ECL Quint 2-Input XOR/XNOR Gate Description The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are

Contextual Info: MC10E166, MC100E166 5V ECL 9-Bit Magnitude Comparator Description The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation.