SHARC 21060 Search Results

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Abstract: ADSP-21000 ADSP-21020 ADSP-21060 ADSP-21061 ADSP-21062
Contextual Info: ADSP-21061 SHARC Preliminary Data Sheet October 1996 For current information contact Analog Devices at 617 461-3881 ADSP-21060/62 SHARC ADSP-21061 ADSP-21061 Super Harvard SHARC Architecture Computer PreliminaryData Information Preliminary Sheet SUMMARY

mercury computer motherboard

Abstract: MCH6 mercury IBM ASIC Products MCH6
Contextual Info: RACE Series SHARC Daughtercard The Analog Devices SHARC DSP processor is one of the highest performing Each SHARC CN contains the following. programmable floating-point DSP proces- SHARC Processors sors in the industry. Mercury takes the Scalable from One to

ADSP-21000

Abstract: ADSP-21060 ADSP-21060L ADSP-21062 ADSP-21062L
Contextual Info: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 a SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,

ADSP-21000

Abstract: ADSP-21060 reference manual ADSP-21062 ADSP-21060 ADSP-21060L ADSP-21062L
Contextual Info: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,

Contextual Info: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica­ tions, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,

Contextual Info: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUM M AR Y High Performance Signal Processor for Com munica­ tions, Graphics, and Imaging Applications Super Harvard ARchitecture Com puter SHARC — Four Independent Buses for Dual Data Fetch,

Contextual Info: Quad-SHARC * DSP Multiprocessor Family AD14060 ANALOG DEVICES PERFORMANCE FEATURES ADSP-21060 Core Processor . . x4 480 MFLOPS Peak, 320 MFLOPS Sustained 25 ns Instruction Rate, Single-Cycle Instruction Execution-Each of Four Processors 16 M b it Shared SRAM (Internal to SHARC™s)

g21k

Contextual Info: ANDIS013 June 1994 ADSP-21060/62 SHARC Preliminary Data Sheet For current information contact Analog Devices at 617 461-3881 ADSP-21060/62 SHARC Super Harvard Architecture Computer SUM M ARY • • • • • High-Performance Signal Processor for Speech, Sound, Graphics, and Imaging Applications

Contextual Info: M/HITE /MICROELECTRONICS W A - A 4 X X X [m o d u là r i ATLAS SHARC 21060 PERIPHERAL PROCESSOR ADVANCED* FEATURES 1553B Remote Terminal/Bus Controller Interface • SHARC 21060 DSP Interface ■ Clock Frequencies: 3 3 ,4 0 MHz 16 Programmable Chip Selects

MO-47AE

Abstract: ADSP-21060L ADSP-21062L EDI8L32128V EDI8L32512V MPC860 TMS320LC31
Contextual Info: EDI8L32512V White Electronic Designs 512Kx32 SRAM Module.3.3V FEATURES    ADSP-21060L SHARC  ADSP-21062L (SHARC)  Texas Instruments TMS320LC31   The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and

ADSP2106XL

Contextual Info: EDI8L32512V K>L 512Kx32SftAMModuk ELECIROMC 0E9GN1 N C 1 Preliminary 512KX32CMOSHigh Speed Static RAM F eatu re s DSP Memory Solution • ADSP-21060L SHARC The EDI8L32512V is a high speed, 3.3V, 16 megabit • ADSP-21062L (SHARC) SRAM. The device is available with access times of 12,

4L4A

Abstract: SHARC 21060
Contextual Info: WHITE M ICRO ELECTRO NICS WH31MXL2X-001X MODULAR HEX21060MODULE, 16M SRAM/16M FLASH ADVANCED* FEATURES FUNCTIONAL DESCRIPTION • SHARC 21060 DSP Based ■ ■ Integra ted C lock G eneration C irc u itry ■ The Hex SHARC 21060 D ig ita l S ignal Processor MCM is a high

JEDECMO-47AE

Contextual Info: ^EDI ED I8L32512V 512Kx32 SRAMModule ELECTRONIC DESIGNS, INC 512Kx32 CMOSHigh Speed Static RAM Features DSP Memory Solution • ADSP-21060L SHARC • ADSP-21062L (SHARC) • TMS320LC31 The ED I8L32512V is a high speed, 3.3V, 16 m egabit SRAM . The device is available w ith access tim es of 12,

Contextual Info: WHITE /M IC R O E L E C T R O N IC S W A-A4XXX ATLAS SHARC 21060 PERIPHERAL PROCESSOR MODULAR ADVANCED * FEATURES • SHARC 21060 DSP Interfa ce 1553B Remote T e rm in a l/B u s C o n tro lle r Interfa ce ■ C lock Frequencies: 33, 40 M H z 16 P rogram m able Chip S elects

60MHZ

Abstract: ADSP-21060L ADSP-21062L EDI8L32128V EDI8L32512V MO-47AE
Contextual Info: White Electronic Designs EDI8L32128V 128Kx32 CMOS High Speed Static RAM FEATURES DESCRIPTION 128Kx32 bit CMOS Static Analog SHARC TM External Memory Solution ADSP-21060L ADSP-21062L Random Access Memory Array Fast Access Times: 12, 15 and 20ns User Configurable Organization

Contextual Info: SHARC Processor SUMMARY KEY FEATURES—PROCESSOR CORE High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch,

60MHZ

Abstract: ADSP-21060L ADSP-21062L EDI8L32128V EDI8L32512V MO-47AE
Contextual Info: White Electronic Designs EDI8L32128V 128Kx32 CMOS High Speed Static RAM FEATURES DESCRIPTION 128Kx32 bit CMOS Static Analog SHARC TM External Memory Solution ADSP-21060L ADSP-21062L Random Access Memory Array Fast Access Times: 12, 15 and 20ns User Configurable Organization

ADSP21000

Abstract: ADSP-21000 ADSP-21060 ADSP-21060C ADSP-21060LC ADSP-21061
Contextual Info: a ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O

adsp 210xx architecture diagram

Abstract: ADSP-21060 reference manual
Contextual Info: BACK a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O

BR46

Abstract: ADSP-21060CZ-160 ADSP-21060LCW-160 ADSP-21060CW-160
Contextual Info: a ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O

adsp 210xx architecture diagram

Abstract: ADSP-21060 reference manual ADSP21000 ADSP-21000 ADSP-21060 ADSP-21060L ADSP-21061 ADSP-21062 64 point FFT radix-4
Contextual Info: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O

ADSP-21060

Abstract: ADSP21000 ADSP-21000 ADSP-21061 ADSP-21062 ADSP-21060 reference manual 74 HTC 08
Contextual Info: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O

adsp 210xx architecture diagram

Abstract: ADSP21000 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-21060LKS-160 parallel port 25 pin connector
Contextual Info: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O

ADSP21060CW160

Abstract: ADSP-21061 ADSP21000 ADSP-21000 ADSP-21060 ADSP-21060C ADSP-21060LC
Contextual Info: a ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O