SIX REASONS Search Results

bcom first year

Contextual Info: Supertex inc. HV9957 Six-Channel LED Driver with Integrated Fault Protection The HV9957 LED driver combines a switch-mode boost converter and six low-dropout linear current regulators to provide the advantages of high efficiency with precise current control.

Contextual Info: Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection * Cypress PREMIS family offering * Generates an EMI optimized clocking signal at the output * Selectable input to output frequency ss% * Six -1.25% , -3.75% , or 0% down spread outputs

HDB3 CODING DECODING FPGA

Abstract: chn 834 chn 832 R13C7 CHN 833 GR-253 GR-253-CORE GR-499-CORE XRT75R06D FPGA AMI coding decoding
Contextual Info: áç XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DECEMBER 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/

W184

Abstract: W185
Contextual Info: W185 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Six –1.25%, –3.75%, or 0% down spread outputs

Contextual Info: W185 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Six –1.25%, –3.75%, or 0% down spread outputs

chn 751

Abstract: GR-253 GR-253-CORE GR-499-CORE XRT75R06D XRT75R06DIB chn 622 st WG 253 chn 834 HDB3 CODING DECODING FPGA
Contextual Info: xr XRT75R06D PRELIMINARY SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER JULY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/

Contextual Info: W184 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable input to output frequency • Six –1.25%, –3.75%, or 0% down spread outputs

H957

Abstract: 825 384 6 TACT2
Contextual Info: Supertex inc. HV9957 Six-Channel LED Driver with Integrated Fault Protection Features XX Drives six strings of LEDs, up to 30mA each XX Phased PWM dimming XX Pin-programmable dimming frequency or synchronizable to an external signal XX PWM dimming to very low duty cycles

Contextual Info: W184 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable input to output frequency • Six –1.25%, –3.75%, or 0% down spread outputs

W184

Abstract: W185 W185-5 hjc 0.1uf
Contextual Info: W185 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Six 1.25%, 3.75%, or 0% down or center spread outputs

CHN 523

Abstract: HDB3 CODING DECODING FPGA chn 752 chn 751 chn 720 GR-253 GR-253-CORE GR-499-CORE XRT75L06D XRT75L06DIB
Contextual Info: xr XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER APRIL 2005 REV. 1.0.4 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line

smps control ic with 8 pin SO

Abstract: H957 RX160
Contextual Info: Supertex inc. HV9957 Six-Channel LED Driver with Integrated Fault Protection Features XX Drives six strings of LEDs, up to 30mA each XX Phased PWM dimming XX Pin-programmable dimming frequency or synchronizable to an external signal XX PWM dimming to very low duty cycles

W184

Abstract: W185 W185-5
Contextual Info: W185 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Six 1.25%, 3.75%, or 0% down or center spread outputs

chn 752

Abstract: HDB3 CODING DECODING FPGA chn 501 chn 732
Contextual Info: XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER OCTOBER 2003 REV. 1.0.2 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line

154407

Abstract: AN378 G747 2039P diode DS1 30PPM DS3112 927p
Contextual Info: Application Note 378 DS3112 Clock Rates www.maxim-ic.com The DS3112 has six different transmit clock and six different receive clock types: transmit DS3, DS2, DS1, E3, E2, and E1 clocks and receive DS3, DS2, DS1, E3, E2, and E1 clocks. Since the clocks at the

W1845

Abstract: W184 W184-5
Contextual Info: W184 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable input to output frequency • Six 1.25%, 3.75%, or 0% down or center spread outputs

W184-5

Abstract: W184
Contextual Info: W184 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable input to output frequency • Six 1.25%, 3.75%, or 0% down or center spread outputs

automotive controller DSRC

Abstract: 8051 edge detection
Contextual Info: USBN9602 USBN9602 Universal Serial Bus Full Speed Function Controller with DMA Support Literature Number: SNOS029A USBN9602 (Universal Serial Bus) Full Speed Function Controller With DMA Support 1.0 General Description Block Diagram CS RD WR trol endpoint EP0 and six FIFOs for an additional six unidirectional Endpoint Pipes to support USB interrupt, bulk and

USBN9602-28M

Abstract: COP888EG CRC16 M28B USBN9602
Contextual Info: USBN9602 Universal Serial Bus Full Speed Function Controller With DMA Support 1.0 General Description Block Diagram CS RD WR trol endpoint EP0 and six FIFOs for an additional six unidirectional Endpoint Pipes to support USB interrupt, bulk and isochronous data transfers. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU

CHN 523

Abstract: CHN 522
Contextual Info: XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER MARCH 2004 REV. 1.0.3 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line Interface Unit LIU for E3/DS3/STS-1 applications.

Contextual Info: Ordering number : ENA0595 Monolithic Linear IC LA6505 For CD-ROM, DVD-ROM and MD players Six-Channel Driver Overview The LA6505 is a six-channel driver for CD and MD players and recorders. It adopts direct PWM drive output in the spindle motor drive to minimize heat generation at high spindle speeds. It also

brushless motors cd rom

Abstract: LA6505 dvd spindle motor driver brushless hall current sensor 3A sanyo sled
Contextual Info: Ordering number : ENA0595 Monolithic Linear IC LA6505 For CD-ROM, DVD-ROM and MD players Six-Channel Driver Overview The LA6505 is a six-channel driver for CD and MD players and recorders. It adopts direct PWM drive output in the spindle motor drive to minimize heat generation at high spindle speeds. It also

diode DS1

Abstract: G747 2039P AN378 APP378 DS3112
Contextual Info: Maxim > App Notes > TELECOM Keywords: DS3112, clock rates, transmit clock, transmit, DS3, DS2, DS1, E3, E2, E1, receive, DS3, DS2, DS1, E3, E2, E1, clocks Dec 06, 2001 APPLICATION NOTE 378 DS3112 Clock Rates and Frequency Tolerances of the Transmit Clock Abstract: The DS3112 has six different transmit clock and six different receive clock types: transmit DS3, DS2,

XAPP623

Abstract: XC3S500E-FT256 simulation model electrolytic capacitor XC3S500E FG256 FT256 UG112 XAPP489 hyperlynx PCB echo sound
Contextual Info: Application Note: Spartan-3E Family R Four- and Six-Layer, High-Speed PCB Design for the Spartan-3E FT256 BGA Package XAPP489 v1.0 October 31, 2006 Summary This application note addresses low-cost, four- to six-layer, high-volume printed circuit board (PCB) layout for a Spartan -3E FPGA in the FT256 1 mm BGA package. The impact of highspeed signals and signal integrity (SI) considerations for low layer count PCB layouts is also