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Catalog Datasheet	MFG & Type	PDF	Document Tags
silego Abstract: Silego Technology D8-D13 D8-D25 Q11A SSTUB32866 lfbga-96ball SLGSSTUB32866B Text: SLGSSTUB32866 DDR2 Configurable Registered Buffer With Parity Applications: • DDR2-400/533/667/800 memory modules • 1:1 25-bit or 1:2 14-bit configurable registered buffer with parity • Able to cascade with a second SLGSSTUB32866 • 1.8V data registers	Original	PDF	SLGSSTUB32866 DDR2-400/533/667/800 25-bit 14-bit SSTUB32866 410MHz 96-LFBGA SLGSSTUB32866 silego Silego Technology D8-D13 D8-D25 Q11A SSTUB32866 lfbga-96ball SLGSSTUB32866B
INSSTE32882 Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B Text: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer	Original	PDF
INSSTE32882 Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877 Text: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer	Original	PDF
silego Abstract: Silego Technology CUA877 SLGUA877B Text: SLGUA877 1.8V PLL Clock Driver for DDR2 Applications: • DDR2-400/533/667/800 memory modules • Zero delay distribution buffers LD,OE OE CONTROL LD,OS,OE LOGIC OS AVDD LD Features: • 1:10 differential clock distribution • Extended Temperature Operation	Original	PDF	SLGUA877 DDR2-400/533/667/800 25MHz-410MHz CUA877 SLGSSTUA32866 silego Silego Technology CUA877 SLGUA877B