SN54LV1 Search Results

SN54LV14

Abstract: 2020CN
Contextual Info: SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS _ S C L S 1 8 7 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-|i Process SN54LV14 . . . J OR W PACKAGE SN74LV14. . . D, DB, OR PW PACKAGE (TOP VIEW) TVplcal V q l p (Output Ground Bounce)

Contextual Info: SN54LV138, SN74LV138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SC LS190P- FEBRUARY 19 9 3 - REVISED JULY 1996 EPIC Enhanced-Performance Implanted CMOS 2-fi Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vc c , Ta = 25°C SN54LV138. . . J OR W PACKAGE

Contextual Info: SN54LV126A, SN74LV126A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES131D – MARCH 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per

Contextual Info: SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402C – APRIL 1998 – REVISED MAY 2000 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per

Contextual Info: SN54LV138A, SN74LV138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS395C – APRIL 1998 – REVISED MAY 2000 D D D D D D description The ’LV138A devices are 3-line to 8-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation. SN54LV138A . . . J OR W PACKAGE

Contextual Info: SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 2 15 3 14 4 13 12 5 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK A B C D ENP 16 CLK CLR NC VCC RCO 1 SN54LV163A . . . FK PACKAGE TOP VIEW 15 RCO 14 QA

SN74LV161

Contextual Info: SN54LV161A, SN74LV161A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4

Contextual Info: SN54LV10A, SN74LV10A TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV163A, SN74LV163A 4ĆBIT SYNCHRONOUS BINARY COUNTERS SCLS405F − APRIL 1998 − REVISED APRIL 2005 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK A B C D ENP 16 CLK CLR NC VCC RCO 1 SN54LV163A . . . FK PACKAGE TOP VIEW 15 RCO 14 QA

Contextual Info: SN54LV175A, SN74LV175A QUADRUPLE DĆTYPE FLIPĆFLOPS WITH CLEAR SCLS400G − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV157A, SN74LV157A QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTORS/MULTIPLEXERS SCLS397F − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D <0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3
Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A

LV125A

Abstract: 74lv125a A115-A C101 SN54LV125A SN74LV125A
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124F – DECEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV125A . . . J OR W PACKAGE SN74LV125A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN54LV138A, SN74LV138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS www.ti.com SCLS395L – APRIL 1998 – REVISED AUGUST 2005 FEATURES SN54LV138A . . . J OR W PACKAGE SN74LV138A . . . D, DB, DGV, NS OR PW PACKAGE TOP VIEW 2 16 15 3 14 4 13 5 12 6 11 7 10 8

Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3ĆSTATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP Output Ground Bounce 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A

LV164A

Abstract: A115-A C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403G − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF

LV125A

Abstract: A115-A C101 SN54LV125A SN74LV125A 74LV125
Contextual Info: SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCES124J – DECEMBER 1997 – REVISED JULY 2003 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A 6

Contextual Info: SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405C – APRIL 1998 – REVISED NOVEMBER 2002 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK A B C D ENP 16 CLK CLR NC VCC RCO 1 15 RCO 14 QA 2 3 A B NC C D 13 QB 12 QC 4 5

A115-A

Abstract: C101 LV123A SN54LV123A SN74LV123A SCLS393O
Contextual Info: SN54LV123A, SN74LV123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS393O − APRIL 1998 − REVISED OCTOBER 2005 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext 1 16

A115-A

Abstract: C101 SN54LV166A SN74LV166A 74lv166
Contextual Info: SN54LV166A, SN74LV166A 8ĆBIT PARALLELĆLOAD SHIFT REGISTERS SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D D Direct Overriding Clear D Parallel-to-Serial Conversion

Contextual Info: SN54LV14A, SN74LV14A HEX SCHMITT-TRIGGER INVERTERS www.ti.com SCLS386 J – SEPTEMBER 1997 – REVISED APRIL 2005 FEATURES 1 • • • • • 2-V to 5.5-V VCC Operation Max tpd of 10 ns at 5 V Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C