SN74AC74 TEXAS Search Results
SN74AC74 TEXAS Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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SN74AC74DBR |
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SSOP -40 to 85 |
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SN74AC74NSR |
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SO -40 to 85 |
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SN74AC74MDREP |
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Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-SOIC -55 to 125 |
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SN74AC74PWR |
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-TSSOP -40 to 85 |
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SN74AC74DR |
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85 |
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SN74AC74 TEXAS Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE |
OCR Scan |
SN54AC74, SN74AC74 SCASS21C- SN54AC74 SN74AC74 | |
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521E – AUGUST 1995 – REVISED NOVEMBER 2002 D D D SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V |
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SN54AC74, SN74AC74 SCAS521E SN54AC74 SN74AC74 | |
AC74Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521D – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V |
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SN54AC74, SN74AC74 SCAS521D SN54AC74 SN74AC74 SN74AC74N SN74AC74NSR SN74AC74PWLE SN74AC74PWR AC74 | |
SN74AC74-EPContextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V |
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SN54AC74, SN74AC74 SCAS521F SN54AC74 SN74AC74-EP | |
AC74
Abstract: SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PWR
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SN54AC74, SN74AC74 SCAS521E SN54AC74 AC74 SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PWR | |
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline |
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SN54AC74, SN74AC74 SCAS521C SN54AC74 SN74AC74 SDYZ001A, 962-88520012A 5962-8852001CA 5962-8852001DA SNJ54AC74FK | |
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline |
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SN54AC74, SN74AC74 SCAS521C SN54AC74 SN74AC74 SN74AC74D SN74AC74DBLE SN74AC74DBR SN74AC74DR SN74AC74N | |
SN74AC74-EPContextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
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SN74AC74EP SCAS721 SN74AC74-EP | |
sac74mep
Abstract: SN74AC74-EP
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SN74AC74EP SCAS721 sac74mep SN74AC74-EP | |
SN74AC74-EPContextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
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SN74AC74EP SCAS721 SN74AC74-EP | |
Contextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
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SN74AC74Ä SCAS721 | |
SN74AC74-EP
Abstract: SN74AC74 SN74AC74MDREP clr 160
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SN74AC74EP SCAS721 SN74AC74-EP SN74AC74 SN74AC74MDREP clr 160 | |
SN74AC74-EPContextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
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SN74AC74EP SCAS721 SN74AC74-EP | |
SN74AC74-EP
Abstract: SN74AC74MDREP SN54AC74 SN74AC74
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SN74AC74EP SCAS721 SN74AC74-EP SN74AC74MDREP SN54AC74 SN74AC74 | |
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SN74AC74 TexasContextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline |
Original |
SN54AC74, SN74AC74 SCAS521C SN54AC74 SN74AC74 Texas | |
AC74
Abstract: SN54AC74 SN74AC74
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SN54AC74, SN74AC74 SCAS521C SN54AC74 AC74 SN54AC74 SN74AC74 | |
SN74AC74-EPContextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
Original |
SN74AC74Ä SCAS721 SN74AC74-EP | |
SN74AC74-EPContextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
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SN74AC74EP SCAS721 SN74AC74-EP | |
SN74AC74-EP
Abstract: SN74AC74 SN74AC74MDREP
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SN74AC74EP SCAS721 SN74AC74-EP SN74AC74 SN74AC74MDREP | |
SN74AC74-EPContextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
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SN74AC74EP SCAS721 SN74AC74-EP | |
SN74AC74-EPContextual Info: SN74AC74ĆEP DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS721 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing |
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SN74AC74EP SCAS721 SN74AC74-EP | |
AC74
Abstract: SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PW
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SN54AC74, SN74AC74 SCAS521F SN54AC74 AC74 SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PW | |
AC74
Abstract: SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PW
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SN54AC74, SN74AC74 SCAS521F SN54AC74 AC74 SN54AC74 SN74AC74 SN74AC74D SN74AC74DBR SN74AC74DR SN74AC74N SN74AC74NSR SN74AC74PW | |
Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE |
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SN54AC74, SN74AC74 SCAS521F |