SN74LS138 Search Results

IC 74LS138

Abstract: connection diagram of ic 74ls138 74s138 SNS4LS138 SN74S138
Contextual Info: TYPES SNS4LS138, SN54S138, SN74LS138, SN74S138 3-LiNE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1 9 7 2 - R E V I S E D A P R IL 1 9 8 5 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 5 4 L S 1 3 8 . S N 5 4 S 1 3 8 . . . J OR W P A C K A G E

Contextual Info: TYPES SN74LS138, SN74S138A, SN54LS138, SN54S138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS DECEMBER 1972 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems REVISED APP 1985 SN54LS138, SN 54S 138A. J PACKAGE SN74LS138, SN74S138A . D OR N PACKAGE

ic 74ls138

Abstract: 74LS138M 74LS139C N74LS139
Contextual Info: TYPES SN54LS138. SN54LS139. SM54S13I, SNS4S139, SN74LS138. SM74LS139, SN74SB8. SN74S139 DECODERS/DEMULTIPLEXERS TTL MSI _ B U L L E T IN NO. DL-S 7611804, D E C E M B E R 1 9 7 2 -R E V IS E O O C T O B E R 1976 • Designed Specifically for High-Speed:

5 to 32 decoder using 4 t0 16 decoders

Abstract: LSI38 sn54138 LS138 SN54LS138 SN54S138 SN74LS138 SN74S138A
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S13BA 3-LINE TO 8 LINE DECODERS/DEMULTIPLEXERS SDLS014 DECEMBER T9 7 2 — REVISED M A R C H 198 8 • Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems • 3 Enable Inputs to Simplify Cascading

74LS138

Abstract: SN74LS138 LS138 SN74LS138N LS04 SN74LS138D SN74LS138DR2 SN74LS138M SN74LS138MEL
Contextual Info: SN74LS138 1-of-8 Decoder/ Demultiplexer The LSTTL/MSI SN74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138

connection diagram of ic 74ls138

Abstract: pin diagram of ic 74ls138 pin for 74LS138 74ls138 function sn54ls138 SN54LS13B 74LS138 function table ic 74ls138 74ls138 74S138A
Contextual Info: SN54LS13B, SN54S138, SN74LS138, SN74S13BA 3 LINE TO 8 UNE DECODERSjDEMULTIPLEXERS DECEMBER 1 9 7 2 -R E V IS E D M AR C H 1 9 8 8 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems SN 5 4 LS 1 38 , S N 54S 138 . . . J OR W PACKAG E

LS138

Abstract: SN74LS138 SN74LS138 datasheet LS04 SN74LS138D SN74LS138N
Contextual Info: SN74LS138 1-of-8 Decoder/ Demultiplexer The LSTTL / MSI SN74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138

SN54138

Abstract: SN74LS138 LS138 SN54LS138 SN54S138 SN74S138A gl 1151
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1972 — R E V IS E D M A R C H 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 54LS 138, S N 54S 138 SN 74LS 138, S N 74S 138A

SN74LS138d

Contextual Info: SN74LS138 1−of−8 Decoder/ Demultiplexer The LSTTL/MSI SN74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138

MC68B21CP

Abstract: xcm916x1cth16 transistor marking code 12W SOT-23 sg379 MC68B54P XC68HC805P18CDW mc68b50cp MC2830 NE555N CHN NE555N
Contextual Info: SG379/D REV 7 Semiconductor Products Sector NORTH AMERICA SALES AND DISTRIBUTION PRICE LIST THIS BOOK IS IN COMPUTER SORT PRODUCT CLASSIFICATION – Please see General Information Section 1.3 EFFECTIVE DATE: JANUARY 10, 1998 General Information 1 Cross References

SN54299

Abstract: LG 21 fs 4
Contextual Info: TLC32044M VOICE-BAND ANALOG INTERFACE CIRCUIT D3495, MAY 1990 Advanced LinCMOS Sllicon-Gate Process Technology J PACKAGE TOP VIEW 14-Bit Dynamic Range ADC and DAC * * * * * * * 16-Bit Dynamic Range Input With Programmable Gain NU[ 1 RESETI 2 e o d r Variable ADC and DAC Sampling Rate up to

SN74299

Abstract: TMS32015 TLC32041 TMS320C17 Frequency-Tracking TLC32040 TLC32040C TLC32040I TLC32041C TLC32041I
Contextual Info: TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995 • • • • • • PART NUMBER DESCRIPTION TLC32040 Analog interface circuit with internal reference. Also a plug-in replacement for TLC32041.

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

JM38510/01405BEA

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 76005012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 7600501EA

TLC32047

Abstract: TLC32047C TLC32047I TMS320 TMS32020 TMS320C25 TMS320C30
Contextual Info: TLC32047C, TLC32047I Data Manual Wide-Band Analog Interface Circuit SLAS049A April 1995 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

68c681

Abstract: FRTX 88C681 XR68C681
Contextual Info: XR68C681 CMOS Dual Channel UART DUART X^EXqR September 1999-2 FEATURES • Two Full Duplex, Independent Channels • Interrupt Vector Output on Acknowledge • Asynchronous Receiver and Transmitter • 8 General Purpose Outputs • Quadruple-Buffered Receiver, Dual Buffered

memory interfacing to mp 8085 8086 8088

Abstract: 82c684cj 82c684 block diagram of processor 80486 intel 8085 and motorola 6800 1C16 LS 74LS138 function and details in microprocessor 8085
Contextual Info: XR -82C 684 C Y V I B t / V i r \ I C M O S Q uad C hannel U AR T Q U A R T August 1997-2 FEATURES • Four Full-Duplex, Independent Channels • Two Multi-function 16-bit Counter/Timers • Asynchronous Receiver and Transmitter • • Quadruple-Buffered Receivers and Transmitters

68C681CJ

Abstract: 68C681 88c681 68c681.h XR-68C681CJ XR68C681
Contextual Info: XR-68C681 CMOS Dual Channel UART DUART August 1997-2 FEATURES • Two Full Duplex, Independent Channels • Interrupt Vector Output on Acknowledge • Asynchronous Receiver and Transmitter • 8 General Purpose Outputs • Quadruple-Buffered Receiver, Dual Buffered

hct 4047 bt

Abstract: SN74ALS679 FCT Fast CMOS TTL Logic 74LS 4075 7804 inverter SN74368A DTL Logic 4069 CMOS hex inverter SN502 CD74AC374
Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

74HCT 4013

Abstract: CD4078 4093 BF SN74368A SN74ALS679 LXZ Series 4069 CMOS hex inverter 2a2 vacuum tube CD74AC374 cd408
Contextual Info: SN54HC240, SN74HC240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS128B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

Contextual Info: SN75ALS171, SN75ALS171A TRIPLE DIFFERENTIAL BUS TRANSCEIVERS SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995 D D D D D D D D D D D D D D D D D DW OR J PACKAGE TOP VIEW Three Bidirectional Transceivers Driver Meets or Exceeds the Requirements of ANSI EIA/TIA-422-B and RS-485 and ITU

Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

std schottky diode SB6

Abstract: 100-W SN75ALS171 SN75ALS171A SN75ALS171ADW SN75ALS171DW SN75ALS171J
Contextual Info: SN75ALS171, SN75ALS171A TRIPLE DIFFERENTIAL BUS TRANSCEIVERS SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995 D D D D D D D D D D D D D D D D D DW OR J PACKAGE TOP VIEW Three Bidirectional Transceivers Driver Meets or Exceeds the Requirements of ANSI EIA/TIA-422-B and RS-485 and ITU

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 76005012A ACTIVE LCCC FK 20 1 TBD 7600501EA ACTIVE CDIP J 16 1 TBD