SN74LV02 Search Results

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390G – APRIL 1998 – REVISED OCTOBER 2002 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC 4Y 1 2 13 4Y 3 12 4B 4 11 4A 5 10 3Y 9 3B 6 7 8 SN54LV02A . . . FK PACKAGE

LV02A

Abstract: A115-A C101 SN54LV02A SN74LV02A
Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

A115-A

Abstract: C101 LV02A SN54LV02A SN74LV02A
Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

LV02A

Abstract: SN54LV02A SN74LV02A
Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390B – APRIL 1998 – REVISED JULY 1998 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE

lv02a

Abstract: A115-A C101 SN54LV02A SN74LV02A
Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

SN54LV02

Abstract: SN74LV02
Contextual Info: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS183B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02, SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES S C L S 1 8 3 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vcc, Ta= 25°C Typical V q h v (Output Vqh Undershoot)

D103D

Abstract: x1sv 199S SN74LV02
Contextual Info: SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATE _SCLS183A - FEBRUARY 1993 - REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CMOS 2-n Process • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vq hv (Output Vq h Undershoot)

Contextual Info: SN54LV02, SN74LV02 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02 . . . FK PACKAGE

LV02A

Abstract: SN54LV02A SN74LV02A
Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390G – APRIL 1998 – REVISED OCTOBER 2002 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC 4Y 1 2 13 4Y 3 12 4B 4 11 4A 5 10 3Y 9 3B 6 7 8 SN54LV02A . . . FK PACKAGE

A115-A

Abstract: C101 LV02A SN54LV02A SN74LV02A
Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390H – APRIL 1998 – REVISED JULY 2003 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC 4Y 1 2 13 4Y 3 12 4B 4 11 4A 5 10 3Y 9 3B 6 7 8 SN54LV02A . . . FK PACKAGE

lv02a

Abstract: A115-A C101 SN54LV02A SN74LV02A 74LV02A
Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390D – APRIL 1998 – REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS390B – APRIL 1998 – REVISED JULY 1998 D EPIC  Enhanced-Performance Implanted D D D D 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A SN54LV02A . . . FK PACKAGE

Contextual Info: SN54LV02A, SN74LV02A QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES SCLS390J − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 13 3 12 4 11 5 10 6 9 7 8 1A 1B 2Y 2A 2B 14 1A 1Y NC VCC