SOT902 Search Results

Contextual Info: XQ FN 8 SOT902-2 XQFN8 U ; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or H Ordering code (12NC) ending 125 Rev. 1 — 2 May 2013 Packing information 1. Packing method Printed plano box Barcode label Reel

Contextual Info: Package outline XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-3 X D A B terminal 1 index area A E A1 detail X e e v w L 4 3 5 2 6 1 7 C C A B C y1 C y b e1 e1 terminal 1 index area 8 metal area not for soldering

Contextual Info: Package outline XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C L y1 C ∅v M C A B ∅w M C 4 y 5 3 metal area not for soldering e1

Contextual Info: XQ FN 8U SOT902-1 XQFN8 U ; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or H Ordering code (12NC) ending 125 Rev. 5 — 2 May 2013 Packing information 1. Packing method Printed plano box Barcode label Reel

Contextual Info: Reflow soldering footprint Footprint information for reflow soldering of XQFN8 package SOT902-3 Hx D 8x 0.025 0.025 C (7×) Hy Ay 1.000 SLy 0.110 0.320 SLx 1.200 solder land solder paste deposit solder land plus solder paste occupied area DIMENSIONS in mm

NXP 12NC ending

Abstract: nxp Tape and Reel Information SOT902-2 SOT902-1 12NC
Contextual Info: SOT902-1 Reversed product orientation 12NC ending 125 Rev. 02 — 28 April 2009 Packing information 1. Packing method Fig. 1 Package version 12NC ending Reel dimensions d x w mm SPQ/PQ (pcs) Reels per box Outer box dimensions l x w x h (mm) SOT902-1 125

Contextual Info: PC board footprint NXP Semiconductors Footprint for reflow soldering of XQFN8 package SOT902-1 1.900 0.450 8x 0.400 (8×) 0.220 (7×) 0.270 (8×) 1.000 1.900 1.200 0.500 0.110 0.320 0.500 1.200 solder lands clearance solder paste placement plus occupied area

Contextual Info: Reflow soldering footprint Footprint information for reflow soldering of XQFN8 package SOT902-2 Hx D 8x 0.025 0.025 C (7×) Hy Ay 1.000 SLy 0.110 0.320 SLx 1.200 solder land solder paste deposit solder land plus solder paste occupied area DIMENSIONS in mm

nz104

Contextual Info: 74LVC2G66 Bilateral switch Rev. 7 — 22 June 2012 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).

MARKING V7 6-PIN

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

Marking code V7

Contextual Info: 74LVC2G00 Dual 2-input NAND gate Rev. 11 — 22 June 2012 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

SOT886

Abstract: BGA Package 0.35mm pitch SOT891 wcsp sot886-1 SOT-902 sot665
Contextual Info: NXP MicroPak and MicroPak II packages for single-, dual-, and triplegate logic functions World’s smallest leadless logic packages MicroPak and MicroPak II packages are the world’s smallest packages for single-, dual-, and triple-gate logic. They are 65% - 74% smaller than their PicoGate equivalents and offer a larger

JESD22-A114E

Abstract: NX3L1G53GD NX3L1G53GM NX3L1G53GT
Contextual Info: NX3L1G53 Low-ohmic single-pole double-throw analog switch Rev. 03 — 17 April 2009 Product data sheet 1. General description The NX3L1G53 provides one low-ohmic single-pole double-throw analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It has a digital select input S ,

74LVC1G53

Abstract: 74LVC1G53DC 74LVC1G53DP 74LVC1G53GD 74LVC1G53GT JESD22-A114E MO-187 V53 TSSOP8
Contextual Info: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 05 — 11 June 2008 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select

74LVC3G14

Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74LVC2G66

Abstract: 74LVC2G66DC 74LVC2G66DP 74LVC2G66GT 74LVCV2G66 JESD22-A114E JESD78
Contextual Info: 74LVC2G66 Bilateral switch Rev. 04 — 1 July 2008 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).

74LVC2G126

Abstract: 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT JESD22-A114E MO-187
Contextual Info: 74LVC2G126 Dual bus buffer/line driver; 3-state Rev. 08 — 5 May 2008 Product data sheet 1. General description The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input pin nOE . A LOW-level at pin nOE

74AUP2G240

Abstract: 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78
Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE

74LVC2G241

Abstract: 74LVC2G241DC 74LVC2G241DP 74LVC2G241GD 74LVC2G241GM 74LVC2G241GT JESD22-A114E
Contextual Info: 74LVC2G241 Dual buffer/line driver; 3-state Rev. 09 — 10 June 2008 Product data sheet 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE:

SOT886

Abstract: sot833 SOT996 SOT-833 2G384 NX3L1G3157GM NX3L1G66GM NX3L1T3157GM NX3L2267GM NX3L4684GM
Contextual Info: NXP’s low-Ohmic switches, the NX3 family Low-Ohmic switches RON value of 0.75 Ω, 0.45 Ω These best in class low-Ohmic switches are an excellent choice for audio and mixed-signal applications in small, portable devices. Our NX3xxT products feature low-switching threshold

LPC2148 i2c

Abstract: BGB210S lpc2148 interfacing 2.8" TFT LCD DISPLAY BGB210 embedded c code to interface lpc2148 with sensor BGW200 TDA8932T tda8920bj NXP PN531 TDA8947J equivalent
Contextual Info: Building blocks for vibrant media Highlights of the NXP product portfolio Building blocks for vibrant media  At NXP Semiconductors, the new company founded by Philips, we’re driven by a single purpose — to deliver vibrant media technologies that create better sensory experiences.

transistor SMD N02

Abstract: NVT2002DP NVT2002GD NVT2002GF NVT2002 JESD22-A114 JESD22-A115 NVT2001 NVT2001GM
Contextual Info: NVT2001; NVT2002 Bidirectional voltage level translator for open-drain and push-pull applications Rev. 1 — 30 August 2010 Product data sheet 1. General description The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V

74LVC2G86

Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT
Contextual Info: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 8 — 19 October 2010 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

74LVC1G74DC

Abstract: 74LVC1G74 74LVC1G74DP 74LVC1G74GD 74LVC1G74GM 74LVC1G74GT
Contextual Info: 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 9 — 5 August 2010 Product data sheet 1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data D inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q