SP16 Search Results

SP1690

Abstract: SP1600 SP1670 SP1600 SERIES ECL III
Contextual Info: SP1690 • PLESSEY SP1600 SERIES SEMICONDUCTORS ECL 111 SP1690 UHF PRESCALER TYPE D FUP-FLOP The SP1690 is a h igh speed D m aster-slave f lip - f lo p ca pa ble o f to g g le rates o v e r 5 0 0 M H 2 . D esigned p r im a r ily f o r h igh P O S IT IV E L O G IC

Contextual Info: SP1670/71 O SP1600 SERIES plessey ECL III SEMICONDUCTORS SP1670 SP1671 HIGH Z (LOWZ) MASTER/SLAVE TYPE D FLIP-FLOP T h e S P 1 6 7 0 /7 1 designed fo r are use in Type D h ig h M aster-slave c o n s tru c tio n M aster-S lave F lip -F lo p s speed d ig ita l

Contextual Info: S P 1 666/7 PLESSEY SP1600 SERIES SEMICONDUCTORS ECL III SP1666 HIGH Z SP1667 (LOWZ) DUAL CLOCKED R-S FUP-FLOP Two Set-Reset flip -flo p s in a single package w hich P O S IT IV E L O G IC require a clo ck in p u t to enable th e set-reset inputs. Internal

SM0402

Abstract: sm3126 Low IF receiver CVHD-950-100 p981 LP3878MR-ADJ no 870 b 2nf 100PF 22PF RD-170
Contextual Info: 1.0 Design Description The SP16130CH4RB Reference Board demonstrates a low IF receiver subsystem application including an ADC16V130 analog-to-digital converter ADC and LMK04031B clock conditioner which provides digitization and clocking as used in wireless infrastructure systems.

c225 diode smd

Abstract: SMD C236 DIODE SB950 Diode 1_b SMD diode C237 Crystek CVHD TSF153F c225 capacitor smd smd schottky diode c148 C241-C243
Contextual Info: National Semiconductor RD-179 High Speed Signal Path Applications October 8, 2009 1.0 Design Description 2.0 Features The SP16160CH1RB demonstrates a high-IF sampling receiver subsystem that provides signal amplification, digitization and clocking as used in wireless infrastructure systems.

Contextual Info: WILLAS FM120-M+ SP1640C THRUTHRU 16.0A SCHOTTKY BARRIER RECTIFIERS -40V- 200V 1.0A SURFACE MOUNT SCHOTTKY BARRIER ITO-220RECTIFIERS PACKAGE-20V- 200V FM1200-M+ SP16200C Pb Free Product SOD-123+ PACKAGE Package outline Features • Batch process design, excellent power dissipation offers

SP1664

Abstract: ECL 10000
Contextual Info: SP1664 FLESSE Y 'w S e m ic o n d u c to rs , SP1664 QUAD 2-INPUT OR GATE The SP1664 com prises fo u r 2-inp ut OR gating fu n c tio n s in a single package. An internal bias reference voltage ensures that the thre shold point remains in the centre of the tran sition

S 890 T

Abstract: SP1668
Contextual Info: SP 1668 A PSLe mEicS SEY W o n d u c to r s SP1668 DUAL CLOCKED LATCH This device is a Dual Clocked Latch/R-S Flip-Flop. Whenever the Clock is low, the R-S inputs control the output stage. Whenever the Clock is high, the output follows the data D input.

SP1674

Contextual Info: SP1674 APLESSEY S em iconductors, SP1674 TRIPLE 2-INPUT EXCLUSIVE-NOR GATE This three gate array is designed to provide the positive logic Exclusive-NOR function in high speed applications. These devices contain a temperature compensated internal bias which insures that the threshold point remains in the

ddgt

Contextual Info: PLESSEY S E MI CO ND UCTOR S TS ~ ]>e | 722DS13 000b7öa S 7220513 P L ES SE Y S EM IC ON D UC TOR S 95D 06780 PLESSEY S e m ic o n d u c to rs . SP1660 DUAL 4-INPUT OR/NOR GATE SP1660 provides simultaneous OR-NOR output functions with the capability of driving 50 mines. This device contains

SP1648

Abstract: SP1648DP DSP1648 plessey 241 B7BB P3400A oscillator plessey
Contextual Info: PLESSEY SE MICON DUC TORS TS DE 1 72EDS13 QQQt.7bl 1 | ~ 7220513 P L E S S E Y S E M I C O ND U C T OR S PLESSEY 95D 06761 D T'SO-/s S e m ic o n d u c to rs . SP1648 ECL OSCILLATOR The SP1648 is an em itter-coupled oscillator, constructed on a single m onolithic silicon chip. O utput levels are

SP16K

Abstract: kmm5362003
Contextual Info: SAMSUNG ELECTRONICS b?E D INC • ? cJbmHH D015BbB bS7 I KMM5362003/G SP16K DRAM MODULES 2M x36 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • P erform ance range: The Samsung KMM5362003/G is a 2M b itx 3 6 Dynamic RAM high density m em ory module. The Samsung

sp1648

Abstract: TRANSISTOR tr4 variable oscillator TR10 TR14 GEC Plessey Semiconductors variable inductor for 100MHz oscillator varactor capacitor diode
Contextual Info: JULY 1994 3028-2.1 SP1648 ECL OSCILLATOR The SP1648 is an emitter-coupled oscillator, constructed on a single monolithic silicon chip. Output levels are compatible with ECL III logic levels. The oscillator requires an external parallel tank circuit consisting of an

Contextual Info: Voltage Transducer LV 100-1000/SP16 For the electronic measurement of voltages: DC, AC, pulsed., with galvanic isolation between the primary circuit high voltage and the secondary circuit (electronic circuit). Electrical data VPN VPM IPN RM with ± 24 V

FSR 400

Abstract: SP1676 SP1676I5
Contextual Info: C ir v a k v w iu w v ^ Corporator ▼ SIGNAL PROCESSING EXCELLENCE SP1676 Series Monolithic 16-bit, 17|as Sampling ADC FEATURES • Com plete 16-bit ADC with Integral Sample/Hold, Reference and Clock ■ ±0.003% FSR Integral Linearity ■ M onotonicity to 14 Bits Over Full

cfl circuit diagram of 12 volts

Abstract: SP1650 cfl circuit diagram of 6 volts SPI650 11-L1 SP1650DG SP1660
Contextual Info: SP1650 A PLESSEY S e m ic o n d u c to rs . SP1650 DUAL A/D COMPARATOR The SP1650 is a very high speed com parator utilising differential am plifier inputs to sense analogue signals above or below a reference level. An output latch provides a unique sam ple-hold feature.

Contextual Info: DATA SHEET SKY13492-21: 0.7 to 2.7 GHz SP16T MIPI Antenna Switch Module Applications • 2G/3G/4G multimode cellular handsets LTE, UMTS, CDMA2000, EDGE, GSM, TDD-LTE, TD-SCDMA  Embedded data cards TRX1 TRX2 TRX3 TRX4 TRX5 Features  Dedicated Band 7 TRX ports: 0.90 dB insertion loss @ 2.7 GHz

SP1600

Abstract: 1672
Contextual Info: or I 0/Z/«5 PLESSEY SP1600 SERIES ECL III SEMICONDUCTORS SP1672 HIGH Z SP1673 (LOWZ) TRIPLE 2-INPUT EXCLUSIVE-OR GATE T h is th re e gate a rra y is desig n ed t o p ro v id e th e p o s itiv e lo g ic E x c lu s iv e -O R fu n c t io n in h igh speed a p p lic a tio n s .

SP16F70

Contextual Info: A F L E S S E Y W Solid State — - SP16F70 MASTER/SLAVE The SP16F70 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP16F70 relatively insensitive to the shape of the clock waveform, since only the voltage levels at

ECL 10000

Abstract: eel -16-2005 "sp-1600" SP1600 SP1664 SP1665
Contextual Info: S P 1 6 6 4 /5 O PLESSEY SP1600 SERIES SEMICONDUCTORS ECL III SP1664 SP1665 HIGH Z (LOWZ) QUAD 2-INPUT OR GATE The SP1664 /5 comprises fo u r 2 -in p u t OR gating fun ctio n s in a single package. A n internal bias reference voltage ensures th a t the threshold p o in t remains in the

TRANSISTOR tr4

Abstract: SP1670 SP1670DG SP1670LC TR23 LC20 TR22
Contextual Info: A FLESSEY W S e m ic o n d u c to rs SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at

SP1600

Abstract: 2sc 1555 SP1660 SP1600 SERIES ECL III
Contextual Info: S P 1 660/1 O PLESSEY SP1600 SERIES SEMICONDUCTORS ECL III SP1660 SP1661 HIGH Z (LOWZ) DUAL 4-IN P U T O R /N O R GATE SP1660/61 provides sim ultaneous O R-NO R o u tp u t functions w ith the capa bility o f driving 5 0 H lines. This device contains an internal bias reference voltage, ensuring

SP1674

Abstract: SP1674DG
Contextual Info: SP1674 âÊh PLESSEY W Semiconductors, SP1674 TRIPLE 2-INPUT EXCLUSIVE-NOR GATE This three gate EC L a rra y is designed to provide the positive logic Exclusive-NOR function in high speed applications. These devices contain a temperature compensated internal bias which ensures that the threshold

SP1666

Contextual Info: SPI 666 m FLESSEY SP1666 DUAL CLOCKED R-S FUP FLOP Two Set-Reset flip-flops in a single package which require a d o ck input to enable the set-reset inputs. Internal input pull-down resistors eliminate the need to return unused inputs to a negative voltage.