SPARTAN-II FPGA Search Results

XC2S100 pq208

Abstract: RS-644 standard intel FPGA SPARTAN XC2S50 FG256 FG676 FT256 PCI33 PQ208 RS-644
Contextual Info: Application Note: Spartan-II and Spartan-IIE Families R Using SelectIO Interfaces in Spartan-II and Spartan-IIE FPGAs XAPP179 v2.1 August 23, 2004 Summary The Spartan -II and Spartan-IIE FPGA families simplify high-performance design by offering SelectIO™ inputs and outputs. The Spartan-II devices can support 16 different I/O standards

XAPP450

Abstract: fpga spartan 2 IN4007 DATASHEET MAX1818 XAPP189 XAPP451
Contextual Info: Application Note: Spartan-II and Spartan-IIE Families R XAPP450 v1.1 October 23, 2008 Summary Power-On Requirements for the Spartan-II and Spartan-IIE Families Contact: Marc Baker Spartan -II and Spartan-IIE FPGAs require a minimum supply current to power on. This

XAPP450

Abstract: Power Current Spartan-IIE MAX1818 XAPP189 XAPP451 OUTPUT SORT CIRCUIT PROTECTION
Contextual Info: Application Note: Spartan-II and Spartan-IIE Families R XAPP450 v1.0 November 15, 2001 Power-On Requirements for the Spartan-II and Spartan-IIE Families Author: Kim Goldblatt Summary Spartan -II and Spartan-IIE Field Programmable Gate Arrays require a minimum supply

256x16* STATIC RAM

Abstract: 32Kx1 false RAMB16 XC2S100 XC2S15 XC2S150 XC2S200 XC2S30 XC2S50
Contextual Info: Single-Port Block Memory Core v6.2 DS234 April 28, 2005 Features • Fully synchronous drop-in module for Virtex , Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Supports all three Virtex-II write mode options:

dc voltage regulator using scr

Abstract: dc voltage regulator circuit using SCR design of mosfet based power supply FPGA programmable switch capacitor Power Current SPARTAN XC2S50 XC2S150 scr power control schematic MAX1818 Si3445DV
Contextual Info: Application Note: Spartan-II and Spartan-IIE Families R XAPP451 v1.0 November 15, 2001 Power-Assist Circuits for the Spartan-II and Spartan-IIE Families Author: Kim Goldblatt, John Rinck, and Hal Sanders Summary Spartan -II and Spartan-IIE Field Programmable Gate Arrays require a minimum supply

2S100

Abstract: SPARTAN-II 2S30 what the difference between the spartan and virtex 2S15 2S50 CS144 FG256 PQ208 TQ144
Contextual Info: Spartan-II Family FAQ 1. What is the Spartan-II family? The Spartan-II family is the next generation family of the Spartan Series based on the industry-leading Virtex architecture. The Spartan-II family extends the portion of the ASIC market that Xilinx can address, while

SPARTAN XC2S50

Abstract: XAPP139 XAPP174 XAPP176 XAPP178 XC2S15 XC2S30 XC4000X XAPP1 8001H
Contextual Info: Application Note: Spartan-II Family Spartan-II FPGA Family Configuration and Readback R XAPP176 v0.9 December 4, 1999 Advance Application Note Summary This application note is offered as complementary text to the configuration section of the Spartan-II data sheet. It is strongly recommended that the Spartan-II data sheet be reviewed

SPARTAN XC2S50

Abstract: XAPP139 XAPP174 XAPP176 XAPP178 XC2S15 XC2S30 XC4000X XC2S50
Contextual Info: Application Note: Spartan-II Family Spartan-II FPGA Family Configuration and Readback R XAPP176 v0.9 December 4, 1999 Application Note Summary This application note is offered as complementary text to the configuration section of the Spartan-II data sheet. It is strongly recommended that the Spartan-II data sheet be reviewed

false

Abstract: DS214 low power and area efficient carry select adder adder xilinx
Contextual Info: Adder/Subtracter v7.0 DS214 April 28, 2005 Product Specification Features • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Generates Adder, Subtracter and Adder/Subtracter

Contextual Info: FD-based Parallel Register v7.0 DS225 April 28, 2005 Product Specification Features • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Supports data from 1 to 256 bits wide

3014 LED

Abstract: XAPP104 XAPP188 SPARTAN XC2S50 XAPP058 XAPP176 XC2S100 XC2S15 XC2S150 XC2S200
Contextual Info: Application Note: Spartan-II Family Configuration and Readback of Spartan-II FPGAs Using Boundary Scan R XAPP188 v2.0 April 19, 2001 Summary This application note demonstrates using a boundary-scan (JTAG) interface to configure and read back Spartan -II FPGA devices. Spartan-II devices have boundary-scan features that

accumulator xilinx v7.0

Abstract: false DS213 low power and area efficient carry select adder
Contextual Info: Accumulator v7.0 DS213 April 28, 2005 Product Specification Features • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Generates Add, Subtract, and Add/Subtract-based

hdlc

Abstract: IEC3309 XF-HDLC RFC1619 XC4000XL HDLC controller CC318f
Contextual Info: HDLC Controller Solutions with Spartan-II FPGAs Customer Tutorial February 2000 File Number Here Agenda Introduction HDLC Overview HDLC Controller Applications Spartan-II IP Solutions for HDLC Controllers HDLC Controller ASSPs Spartan-II Family - Programmable ASSP

SPARTAN XC2S50

Abstract: CS144 FG256 PCI33 PQ208 TQ144 VQ100 XAPP179 XC2S15
Contextual Info: Application Note: Spartan-II Family Using SelectI/O Interfaces in Spartan-II FPGAs R XAPP179 v1.0 November 30, 1999 Application Note Summary The Spartan -II FPGA family simplifies high-performance design by offering SelectI/O™ inputs and outputs. The Spartan-II devices can support 16 different I/O standards with different

17s15

Abstract: SPARTAN-II xc2s200 XC2S150 17S100A
Contextual Info: Spartan-II Family of One-Time Programmable Configuration PROMs XC17S00A R DS078 (v1.4) October 9, 2001 5 Introduction Advance Product Specification Spartan-II PROM Features Spartan -II The family of PROMs provide an easy-to-use, cost-effective method for storing Spartan-II device configuration bitstreams.

XC17S200APDG8I

Abstract: 17S200A SPARTAN XC2S50 XC17S200APDG8 XC17S200APDG8I pin one XC17S200APD8C 17S200 XC17S00A XC2S100 XC2S15
Contextual Info: Spartan-II/Spartan-IIE Family OTP Configuration PROMs XC17S00A R DS078 (v1.10) June 25, 2007 Product Specification 5 Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan -II/Spartan-IIE FPGA devices

xilinx MARKING CODE

Abstract: XC17S150APD8C HW-130 Programmer 17S15A XC2S150 17S50A
Contextual Info: Spartan-II Family of One-Time Programmable Configuration PROMs XC17S00A R DS078 (v1.3) June 20, 2001 5 Introduction Advance Product Specification Spartan-II PROM Features Spartan -II The family of PROMs provide an easy-to-use, cost-effective method for storing Spartan-II device configuration bitstreams.

17S15A

Contextual Info: Spartan-II Family of One-Time Programmable Configuration PROMs XC17S00A R DS078 (v1.1) November 13, 2000 5 Introduction Advance Product Specification Spartan-II PROM Features Spartan -II The family of PROMs provide an easy-to-use, cost-effective method for storing Spartan-II device configuration bitstreams.

17s50a

Abstract: 17S200A
Contextual Info: Spartan-II Family of One-Time Programmable Configuration PROMs XC17S00A R DS078 (v1.2) April 7, 2001 5 Introduction Advance Product Specification Spartan-II PROM Features Spartan -II The family of PROMs provide an easy-to-use, cost-effective method for storing Spartan-II device configuration bitstreams.

XAPP174

Abstract: CLK180 SRL16 UG331 XAPP132 XAPP176
Contextual Info: Application Note: Spartan-II/IIE FPGAs R XAPP174 v1.2 June 16, 2008 Using Delay-Locked Loops in Spartan-II/IIE FPGAs Summary The Spartan -II and Spartan-IIE FPGA families provide four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits, which provide zero propagation delay, low clock skew

verilog code of sine rom

Abstract: sine wave output for fpga using verilog code vhdl code for 555 DS275 X9111 SPARTAN 6 verilog code for sine wave output using FPGA verilog code for sine wave using FPGA
Contextual Info: Sine/Cosine Look-Up Table v5.0 DS275 April 28, 2005 Product Specification Features Functional Description • Drop-in module for Virtex , Virtex-E, and Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs The Sine/Cosine module accepts an unsigned input

vhdl code for msk modulation

Abstract: vhdl code to generate sine wave vhdl code dds XILINX vhdl code NCO DS246 equivalent verilog code for sine wave using FPGA DS246 verilog for 8 point fft using FPGA spartan3 verilog code to generate sine wave XIP166
Contextual Info: DDS v5.0 DS246 April 28, 2005 Product Specification Features • • • • • • • • • • • • • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs Sine, Cosine, or quadrature outputs

XC3S600E

Abstract: XAPP176 SPARTAN XC2S50 XAPP178 16CLB xapp138 XAPP174 XAPP188 XC17S00A XC2S15
Contextual Info: Application Note: Spartan-II and Spartan-IIE Families R XAPP176 v1.1 June 13, 2008 Configuration and Readback of the Spartan-II and Spartan-IIE FPGA Families Summary This application note is offered as complementary text to the configuration sections of the

XAPP058

Abstract: XAPP188 SPARTAN XC2S50 Spartan-II XAPP176 XC2S100 XC2S100E XC2S15 XC2S150 XC2S200
Contextual Info: Application Note: Spartan-II and Spartan-IIE Families Configuration and Readback of Spartan-II and Spartan-IIE FPGAs Using Boundary Scan R XAPP188 v2.3 June 20, 2008 Summary This application note demonstrates using a Boundary-Scan (JTAG) interface to configure and