SRAM IP Search Results

28F3202C3

Abstract: 29066
Contextual Info: PRODUCT PREVIEW 3 VOLT ADVANCED+ STACKED CHIP SCALE PACKAGE MEMORY 16-Mbit Flash + 2-Mbit SRAM - 28F1602C3 16-Mbit Flash + 4-Mbit SRAM - 28F1604C3 32-Mbit Flash + 4-Mbit SRAM - 28F3204C3 32-Mbit Flash + 2-Mbit SRAM - 28F3202C3 ! Flash Memory Plus SRAM

TCAM

Abstract: nP3400 PB3450 nP3450 amcc np3400
Contextual Info: nP3450 Advanced Product Brief 4.4Gbps Integrated Network Processor and Traffic Manager PB3450 / V0.3 / 04/24/2003 • Switched Ethernet Platforms • Ethernet Over SONET/SDH • CPE Equipments, MTU/MDU SRAM SRAM SRAM SRAM/ TCAM Applications Features 24 FE

tcam

Abstract: MPLS nP3450 NP3454 nP3400 amcc np3400 np3404
Contextual Info: nP3454 Advanced Product Brief PB3454 / V0.3 / 04/24/2003 4.4Gbps Integrated Network Processor and Traffic Manager SRAM SRAM SRAM SRAM/ TCAM Applications • Switched Ethernet Platforms • Ethernet Over SONET/SDH • CPE Equipments, MTU/MDU Features 2 GE nP3454

AG29

Abstract: ipug45_01.5 transistor w1d transistor w4B SRAM SAMSUNG FC1152 3ah22
Contextual Info: ispLever CORE TM QDRII+ SRAM Controller MACO Core User’s Guide June 2008 ipug45_01.5 QDRII+ SRAM Controller MACO Core User’s Guide Lattice Semiconductor Introduction Lattice’s QDRII and QDRII+ QDRII/II+ SRAM Controller MACO core assists the FPGA designer’s efforts by

mt90c

Abstract: MT56C0816EJ-25 mt56c0816
Contextual Info: MICRON TECHNOLOGY INC SSE T> WÊ blllSHT 0 0 0 3 ^ 3 7HT B U R N MT56C0816 8K x 16, DUAL 4K x 16 CACHE DATA SRAM V H C Z R O N CACHE DATA SRAM SINGLE 8Kx 16 SRAM, DUAL4KX16 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 16 SRAMs with common

ic 4082 16 pins

Abstract: ic 4082 ic 4082 and pin configuration
Contextual Info: IP X fd t Integrated Ete1i'ice Technology, Inc. Inf7MBV4150 128K x 64/256K x 72 SYNC HR ON OUS PIPELINED BU RST SRAM 256K x 72 BU RST Z B T SRAM MODULE FAMILY IDT7MBV4151 IDT7MBV4152 FEATURES: DESCRIPTION: • Pin compatible module family for pipelined burst SRAM and

Contextual Info: 8 Megabit Flash + 2 Megabit SRAM ComboMemory SST32LH802 Advance Inform ation FEATURES: • Organized as 512 K x16 Flash + 128Kx16 SRAM or 512K x8 x2 Flash + 128K x8 x2 SRAM • Single 3.0-3.6V Read and Write Operations • Concurrent Operation - Read from or write to SRAM while erase/

jmicron

Abstract: MT58C1
Contextual Info: SSE D MICRON TECHNOLOGY INC IC R O N • b l l i s m 0005^53 LIT 16K X IPIRN MT58C1616 DIE 16 SYNCHRONOUS SRAM -T MILITARY SRAM DIE 16Kx 16 SRAM WITH CLOCKED, REGISTERED INPUTS FEATURES • • • • • • • • Fast access times: 20,25 and 35ns

Contextual Info: TOSHIBA TH50VSF1302/1303AAXB TOSHIBA MULTI CHIP INTEGRATED CIRCUIT TENTATIVE SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI CHIP PACKAGE DESCRIPTION The TH50VSF1302/1303AAXB is a package of mixed 2,097,152-bit SRAM and 8,388,608-bit FLASH memory. The SRAM and FLASH memory organized 262,144 words by 8 bits SRAM and 1,048,576

Contextual Info: TOSHIBA TH 50VSF1320/1321AAXB TENTATIVE TOSHIBA MULTI CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI CHIP PACKAGE DESCRIPTION The TH50VSF1320/1321AAXB is a package of mixed 2,097,152-bit SRAM and 8,388,608-bit FLASH memory. The SRAM and FLASH memory organized 262,144 words by 8 bits SRAM and 1,048,576

Contextual Info: MICRON TECHNOLOGY INC SSE ]> b i l l i g 0004GGS ¿OI MICRON 256K X IPIRN MT8S25632 32 SRAM MODULE - ' " P J t - i ' 5 - 1 4 SRAM MODULE 256K X 32 SRAM FEATURES • High speed: 15*, 20,25 and 35ns • High-density 1MB design • High-performance, low-power, CMOS double-metal

Contextual Info: LatticeMico Asynchronous SRAM Controller The LatticeMico asynchronous SRAM controller is a slave device for the WISHBONE architecture. It interfaces to an industry-standard asynchronous SRAM device. Version This document describes the 3.2 version of the LatticeMico asynchronous

ISSI Signs SRAM Technology Licensing Agreement with IBM

Abstract: Licensing Agreement with IBM
Contextual Info: ISSI Signs SRAM Technology Licensing Agreement with IBM SAN JOSE, Calif., Feb. 27, 2012 - ISSI has signed a technology licensing agreement with IBM around SRAM technology, enhancing a relationship that started in 2004 for SRAM technology. Said Tom Reeves, VP of Business Development and Licensing, at IBM: "IBM has a rich and extensive IP portfolio in

Contextual Info: TOSHIBA TH 50VSF1 3 2 0 /1 3 2 1AAXB TENTATIVE TOSHIBA MULTI CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI CHIP PACKAGE DESCRIPTION The TH50VSF1320/1321AAXB is a package of mixed 2,097,152-bit SRAM and 8,388,608-bit FLASH memory. The SRAM and FLASH memory organized 262,144 words by 8 bits SRAM and 1,048,576

MTSC1008

Abstract: micron sram DDD347D MT5C1008 MT5C1008DJ-25 5A143 MT5C100B IA15I 81A12
Contextual Info: MICRON TE C H N O L O G Y INC M I C R O t i l l 5 in Q 0 034b4 Oñb SSE » MT5C1008 128K X 8 SRAM N SRAM 128K x 8 SRAM 5 VOLT SRAM WITH OUTPUT ENABLE FEATURES • High speed: 12*, 15*, 17,20,25,35 and 45ns • High-performance, low-power, CMOS double-metal

Contextual Info: Rev 2; 5/06 DS2045W 3.3V Single-Piece 1Mb Nonvolatile SRAM The DS2045W is a 1Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

Contextual Info: Rev 1; 5/06 DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM The DS2065W is a 8Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

DS2045AB

Abstract: DS2045AB-100 DS2045AB-70 DS2045Y DS2045Y-100 DS2045Y-70 DS80C390 DS2045
Contextual Info: Rev 0; 10/04 DS2045Y/AB Rechargeable 1M Nonvolatile SRAM Features The DS2045 is a 1Mb rechargeable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

DS1270W

Contextual Info: Rev 0; 8/06 3.3V Single-Piece 16Mb Nonvolatile SRAM Features The DS2070W is a 16Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

qdrii sram

Contextual Info: QDRII SRAM Controller MegaCore Function Errata Sheet December 2006, MegaCore Version 6.1 This document addresses known errata and documentation issues for the QDRII SRAM Controller MegaCore function version 6.1. Errata are functional defects or errors, which may cause the QDRII SRAM

Contextual Info: Rev 2; 5/06 DS2045L 3.3V Single-Piece 1Mb Nonvolatile SRAM The DS2045L is a 1Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

Contextual Info: PRELIMINARY MT58LC64K32D9 64KX 32 SYNCBURST SRAM MICRON • lfcCHNOlOGY. INC. 64K x 32 SRAM + 3 .3 V S U P P L Y , P IP E L IN E D , S IN G L E -C Y C L E D ES ELEC T AND SELECTABLE BURST M O DE NEW SYNCHRONOUS SRAM FEATURES • • • • • • • •

DS1270W

Abstract: DS2070W-100 DS2070W
Contextual Info: Rev 0; 8/06 3.3V Single-Piece 16Mb Nonvolatile SRAM Features The DS2070W is a 16Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

ModelSim

Contextual Info: QDRII SRAM Controller MegaCore Function Errata Sheet June 2007, MegaCore Version 7.1 This document addresses known errata and documentation issues for the QDRII SRAM Controller MegaCore function version 7.1. Errata are functional defects or errors, which may cause the QDRII SRAM