SS6303 Search Results

Contextual Info: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ i^ ^ _ S C A S M 6 C - F E B R U A R Y 1 9 9 3 -R E V IS E D N O V E M B E R 1996 « Low Output Skew for Clock-Distributlon and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes One Clock Input to Twelve

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Abstract: SN74AS304 7828S 7520B "Clock Drivers"
Contextual Info: SN74AS304 OCTAL DIVIDE-BY-2 CIRCUITS/CLOCK DRIVERS D 3555. JU LY 1990 Maximum Output Skew of 1 ns D OR N PACKAGE TOP VIEW Maximum Pulse Skew of 1 ns Q3[ Q4[ GND[ GND[ GND[ 1 U 2 3 4 5 Q5[ 6 Q6[ 7 Q7[ 8 Center-PIn V qc and GND Configurations to Minimize High-Speed Switching Noise

Contextual Info: SN54ALS996, SN74ALS996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES SDAS098B - OCTOBER 1 984- R EVISED JANUARY 1996 SN64ALSM0. JT PACKAGE SN74ALSSM . DW OR NT PACKAGE TOP VIEW ^-State l/O-Type Read-Back Inputs Bus-Structured Pinout T/C Determines True or Complementary