STATI Search Results

TC9303AN

Abstract: 6LW6 TC9303 tc9304f LCD12 TC9319F TC9301AN TC9309F
Contextual Info: Digital Tuning System DTS (1) System IC-LSI System No. Controller PLL prescaler DTS-9 A3 Operating Voltage Crystal Oscittation TC9301AN TC9172AP 4.5-5.5V 7.2MHz TC9303AN TC9227P 4.5-5.5V 7.2MHz Major Functions Receiving Band Preset Memory * Station Clock

Contextual Info: TC55417P/J —15H. TC55417P/J-20H TC55417P/J—25H. TC55417P/J-35H • * 16,384 W O R D x 4 BIT CMOS STATIC RAM DESCRIPTION The TC55417P/J—H is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits using CMOS technology, and operated from a single 5 - volt supply.

ic tl 741

Abstract: S47C256
Contextual Info: AD V A N C E INFORM ATION TM S47C256 32,768-W ORD BY 8-BIT R EAD -O N LY M EM O R Y NOVEM BER 1 9 8 5 3 2 ,7 6 8 X 8 Organization N PACKAGE TOP VIEW Fully Static (No Clocks. No Refresh) NC C 1 y j 2 Q : 27 : A12 C 2 A7 C 3 26 : All Inputs and Outputs TTL Compatible

260-pin

Contextual Info: TOSHIBA TC55V1864J/FT-10/12/15 PRELIMINARY SILICON GATE CMOS 65,536 WORD x 18 BIT CMOS STATIC RAM Description TheTC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits and operated from a single 3.3V : upply. Toshiba’s advanced CMOS technology and circuit design enable high speed operation.

Contextual Info: • ■ ! ■ ■ ■ ■ • '|<f TOSHIBA MIOS MEMORY PRODUCTS 8,192 WORD X 8 BIT CM OS STATIC RAM SILICON GATE C M O S T C 5 5 63 A P L-1 0, T C 5563A P L-12 T C 55 6 3 A P L -1 5 DESCRIPTIO N The TC5563APL is 65,536 bit static random access memory organized as 8,1 92 words by 8 bits

Contextual Info: TT ï>Ëf| TOT755O 0D17554 S 990 17224 9097250 TOSHIBA <DISCRETE/OPTO D"T-m-33 TLR358, TLR359, TLR328, TLR329 • RED Color, 13.5ao o.;53")Charactec Height Numerical Display. • Pin Connections for Static Drive • Available Both Polarity of Connections, Common Cathode or Coanon Anode.

TLR4202

Abstract: TLC2207 TL6220 TLR2207 TLC2177 TL62207/TLR2207
Contextual Info: T TOSHIBA {DISCRETE/OPTO} 9097250 T O S H IB A 99D < D IS C R E T E /O P T O 17259 D T -4 1 -S3 TLG2 I77, TLG4 I72, TLG2207, TLG4202 GREEN COLOR 4 D IG IT S L E D D IS P L A Y * For uje of Static drive connections and available both polarity coonon anode or

TC528257

Abstract: n724
Contextual Info: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS multiport m em ory equipped with a 262,144-w ords by 8 -bits dynam ic random access m em ory RAM port and a 512-words by 8 -bits static serial access m emory (SA M ) port. The

UM61256FK-15

Abstract: um61256fs 15 UM61256FS-15 um61256f um61256fk15 UM61256FK UM61256FM-25 um61256 UM61256FK-12 um61256fs
Contextual Info: UM61256F Seríes 32K X a High Speed CMOS SRAM Features • * ■ ■ ■ Single +5V power supply ■ Access times: 12 /15/2 5 ns max. ■ Current: Operating: 150mA (max.) Standby: 12mA (max.) ■ Full static operation, no clock o r refreshing required Directly TTL compatible: All inputs and outputs

lt928

Abstract: 55328P TC55328J
Contextual Info: 3 2 ,7 6 8 W O R D x 8 B IT C M O S S TA TIC R A M D E S C R IP T IO N The TC55328P/J is a 262,144 bits high speed static random access memory organized as 32,768 words by 8 bits using CMOS technology, and operated from a single 5-volt supply. Toshiba's CMOS

Contextual Info: SN54ALVTH16652, SN74ALVTH16652 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCES192 - FEBRUARY 1999 State-of-the-Art Advanced BiCMOS Technology ABT Widebus Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation

Contextual Info: TOSHIBA TC55V1664J/FT-10/12/15 PRELIMINARY SILICON GATE CMOS 65,536 WORD x 16 BIT CMOS STATIC RAM Description The TC55V1664J/FT is a 1,048.5,'6 bit high speed CMOS static random access memory organized as 65,536 words by 16 bits and operated from a single 3.3V sjpply. Toshiba's advanced CMOS technology and circuit design enable high speed operation.

Contextual Info: Tem ic 80C32/80C52 Semiconductors CMOS 0 to 44 MHz Single Chip 8-bit Microcontroller 1. Description TEMIC’s 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit Microcontroller. The fully static design of the TEMIC 80C52/80C32

LQFP-100

Contextual Info: TOSHIBA TC55WD1618FF-133,-150,-167 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TENTATIVE SILICON GATE CMOS 1,048,576-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM DESCRIPTION The TC55WD1618FF is a synchronous static random access memory SRAM organized as 1,048,576 words by

a14 Transistor

Contextual Info: TEXAS XNSTR QbE D | 011.1751 0075454 5 | SM61CD64, SMJ61CD64 65.536-W0RD BY 1-BIT STATIC RAMS Separate I/O J D PA C K A G E TOP VIEW AOC A1C A2C A3Q A4Q A5Q A6^ Military Temperature Range . . . -5 5 ° C to 125°C (M Suffix) • • Fast Static Operation

UM621024B

Abstract: UM621024 um621024bm-70l
Contextual Info: UM621024B Seríes 128K X 8 CMOS SRAM Features • Single +5V power supply ■ Access times: 55/70 ns max. ■ Current: Low power version: Operating: 70mA Standby: 100(iA Very low power version: Operating: 70mA Standby: 25 (¿A * Full static operation, no clock or refreshing

44LSO

Contextual Info: UM23L64100 4,1 9 4 ,3 0 4 X 16/8,388,608 X 8 BIT LOW VOLTAGE CMOS M ASK ROM P R E LIM IN A R Y Features • 4,194,304 x 1 6 /8 ,3 88 ,6 0 8 x 8-bit o rga n izatio n 1 Full static ope ra tio n ■ S ing le + 3 V p o w e r su pp ly 1 T T L-co m p atib le inputs and o utp uts

Contextual Info: SMJ684002 512K BY 84HT STATIC RANDOM-ACCESS MEMORY _ * Single 5-V ± 10% Power Supply HJA/HKE PACKAGE TOP ViEW f • • Fast Access Time 20125/35 ns Equal Address and Chip-Enable Access Time • • • All Inputs and Outputs Are TTL-Compatible

Contextual Info: TMS47128 16,384-WORD BY 8-BIT READ-ONLY MEMORY JU N E 1 9 8 3 - N PACKAGE 1 6 ,3 8 4 X 8 Organization TOP VIEW Fully Static (No Clocks, No Refresh) NC £ 1 All Inputs and Outputs TTL Compatible 2 8 3 V CC 2 7 3 S 2 /S 2 A 12 £ 2 A 7C 3 Single 5-V Power Supply

UM61M512K-15

Abstract: UM61M512K15 UM61M512 um61M512K UM61M512-20 um61m UM61M51
Contextual Info: UM61M512 Seríes 64KX 8, 3.3V I/O High Speed CMOS SRAM Features • Single +5V power supply * Access times: 15/20 ns max. ■ Current: Operating: 160mA (max.) Standby. 10mA (max.) ■ Full static operation, no clock or refreshing required ■ 3.3V I/O com patible

TMS47C256 ROM

Contextual Info: TE XA S INS TR -CASIC/NEHORY} 77 ADVANCE INFORMATION 0^1725 DE 0040=107 4 | ~ TMS47C256 32,768-WORD BY 8-BIT READ-ONLY M EM O RY NOVEMBER 1985 N PACKAGE • 32,768 X 8 Organization • Fully Static No Clocks, No Refresh • All Inputs and Outputs TTL Compatible

Contextual Info: TC5050P C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC5050P DUAL 50/64 STAGE STATIC SHIFT REGISTER T C5050P is static shift register consisting of D type flip-flops, and can be used as e i ther 50 bit shift register or 64 bit shift register d e pending on OUTPUT

Contextual Info: 7. COMMON EL ECT RI CA L CHA RA C TE RI ST IC S 7 -1 P o w sr D issip ation The power dissipation of CMOS device is composed of two components: one static, the other dynamic. The total power dissipation is the sum of static and dynamic power dissipation. Static power dissipation is obtained by multiplying quiescent supply current by the supply voltage range

TC55188

Abstract: TC55188T-25 TC55188T-20 TC55188T
Contextual Info: •»ilK 2 - W A Y 4,096 W ORDS x 18 BITS/8,192 WORDS x 18 BITS CMOS STATIC CACHE DATA RAM DESCRIPTION The TC55188T is a 147,456bits high-speed static RAM which can be user-configured either a s 2-way 4,096 words by 18 bits or as 8,192 words by 18 bits. It is provided with a byte control, on-chip