STM0 MAPPER Search Results

user manual of XRT91L31

Contextual Info: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to

XRT91L31

Contextual Info: XRT86SH328 SONET TO 28-T1/21-E1 PDH MAPPER - VOYAGER PIN AND ARCHITECTURE DESC JUNE 2010 REV. 2.0.0 GENERAL DESCRIPTION The XRT86SH328 Voyager is a physical layer SONET/SDH to PDH mapper/demapper which enables T1/E1 aggregation to STS-3/STM-1 or STS1/ STM0 via standard VT1.5/VT2 or VC-11/VC-12 to

i750

Abstract: TSK1V AU-AIS X0055 PCM30 XRT86SH221 XRT86SH221IB ASA17 intel i860
Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU MAY 2007 REV. P1.0.5 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

SDH 209

Abstract: T85 Slide Switch X0055 6 PORT LIU capacitor 102 STM P1875 MCP860 diagram circuits power supply APS 283 49mhz remote control transmitter circuit AU-AIS
Contextual Info: XRT86SH221 SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU AUGUST 2008 REV. 1.0.1 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

PCM encoder circuit ami

Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU MARCH 2007 REV. P1.0.4 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

0X029E

Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU NOVEMBER 2007 REV. P1.0.8 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

code h1a

Contextual Info: XRT86SH221 SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU FEBRUARY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU SEPTEMBER 2007 REV. P1.0.7 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

0x0203

Abstract: 21-CHANNEL
Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU NOVEMBER 2006 REV. P1.0.2 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

VT138

Abstract: ASA17
Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH SEPTEMBER 2006 REV. P1.0.1 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

VT210

Contextual Info: XRT86SH221 PRELIMINARY SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU AUGUST 2007 REV. P1.0.6 GENERAL DESCRIPTION The XRT86SH221 Voyager-Lite is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3

25e5

Abstract: GR253-CORE GR-253 TMPR28051 VT13 GR-253 J0 byte length 14
Contextual Info: Advisory August 5, 1999 TMPR28051 STS-1/AU-3 STM-0 Mapper Device Advisory for Version 5 of the Device Register Architecture (RA) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L.

GR-253

Abstract: TMPR28051
Contextual Info: Advisory August 5, 1999 TMPR28051 STS-1/AU-3 STM-0 Mapper Device Advisory for Version 5 of the Device Register Architecture (RA) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L.

X1HB

Abstract: telecom bus DM9000 application Digital Alarm Clock by using ttl LXT6251A 001H LXT6051 MTD10 LXT6282 MTC11
Contextual Info: LXT6251A 21 E1 SDH Mapper Datasheet The LXT6251A 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard Telecom bus interface. Further processing by the companion

TUG-3

Abstract: SDH ADM AU-3 63xE1 Exar cross mapping TU12 XRT86SH221 XRT86SH221IB TU-12
Contextual Info: XRT86SH221 Voyager Lite SDH to PDH Framer/Mapper with Integrated 21 Channel E1 LIU Ideal for Cost-Sensitive Transport Applications Including Multi-service Provisioning Platforms and Routers T he XRT86SH221 (Voyager Lite) is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to

hdlc

Abstract: PM5383 PM8316 E1 frame POS-PHY ATM format
Contextual Info: PM5383 S/UNI 12xJET Preliminary 12-Channel ATM and Bit HDLC User Network Interface MODES OF OPERATION FEATURES • Single chip 12-channel DS3/E3/J2 framer and ATM / bit-HDLC mapper into POS-PHY / UTOPIA interface. Each channel can be individually configured for the desired rate and

LED VIPER

Abstract: VIPER IC AU-AIS GI 312 diode transistor st 431 SDH 209 sf 118 d SF 119 D viper 504 VIPer Design Software
Contextual Info: XRT94L31 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S D H R E G S T E R M A P CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– S SD DH HR RE EG GIIIS ST TE ER RM

E1 to fiber optic converter circuit

Abstract: stm-1 nortel BTS ericsson LP-UNEQ ERICSSON BTS product LP-UNEQ STM-1 HDB3 and CMI which is better Ericsson Base Station G-783 vc-4 digital cross connect
Contextual Info: LXT6051/LXT6251 SDH Chipset SDH and ITU Standards Application Note January 2001 Order Number: 249311-001 As of January 15, 2001, this document replaces the Level One document known as AN9801. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

E1 to fiber optic converter circuit

Abstract: LEVEL ONE COMMUNICATIONS SSI 7200 sxt multiplexer LP-UNEQ microwave movement detection 2E11-1 2E111 Signal path designer
Contextual Info: Application Note 9801 SXT6051/SXT6251 SDH Chipset FEBRUARY 1998 Revision 1.0 SDH Specifications and ITU Standards SDH and ITU Specifications The original goal of the Standards Committee was to establish an international specification for a common hierarchy

san francisco telecom

Abstract: X1HB 001H MTC21 SXT6251 MTC11 MTD16 P1396 MTC13 MTC15
Contextual Info: DATA SHEET MAY 1998 Revision 1.1 SXT6251 21 E1 SDH Mapper General Description Features The SXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard Telecom

diode DS1

Abstract: GR253-CORE ETS300 GR-253 T7693 TMPR28051 TMUX03155 STM0 mapper
Contextual Info: Product Brief September 1999 TMPR28051 STS-1/AU-3 STM-0 Mapper Features • Maps signals in one of the following ways: — Maps up to 28 asynchronous DS1 signals to SONET STS-1 via VT Groups, or SDH AU-3 via TUG-2. — Maps up to 21 asynchronous E1 signals to SDH

0x1758

Abstract: AU-AIS GR-253-CORE XRT94L33 XRT94L33IB ST VIPER application notes 0x11B3 574 91 256
Contextual Info: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S D H R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– S SD DH HR RE EG GIIIS ST TE ER RS S March 2007

AU-AIS

Abstract: Digital Alarm Clock by using ttl LXT e2 LXT6251A marking cod A2 regenerator in optical D4D12 LXT6051 LXT6051QE SSI 7200
Contextual Info: LXT6051 STM-1/0 SDH Overhead Terminator Datasheet The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0 51Mb/s and STM-1 (155Mb/s) multiplexers. It provides micro-controller access for performance monitoring,

Contextual Info: XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC OCTOBER 2006 GENERAL DESCRIPTION The XRT94L31 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream. The XRT94L31 interfaces directly to the