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16F15

Abstract: L4C381-15
Contextual Info: L4C381 L4C381 DEVICES INCORPORATED 16-bit Cascadable ALU 16-bit Cascadable ALU DEVICES INCORPORATED FEATURES DESCRIPTION ❑ High-Speed 15ns , Low Power 16-bit Cascadable ALU ❑ Implements Add, Subtract, Accumulate, Two’s Complement, Pass, and Logic Operations

Contextual Info: FEATURES DESCRIPTION □ 45 ns Multiply-Accumulate Time □ Low Power CMOS Technology □ Replaces TRW TDC1009/TM C2009 □ Tw o's Complement or Unsigned Operands □ Accumulator Performs Preload, Accumulate, and Subtract □ Three-State Outputs □ DESC SMD No. 5962-90996

am9511A

Abstract: AM9511 FLOATING POINT Co Processor 9511A
Contextual Info: Am9511A Arithmetic Processor Am9511A MILITARY INFORMATION DISTINCTIVE CHARACTERISTICS 2 and 3 MHz operation; fixed point 16-bit and 32-bit operations Floating point 32-bit operations; binary data formats Add, Subtract, Multiply and Divide; trigonometric and

L4C381

Abstract: L4C381GC L4C381GC26 p15c0
Contextual Info: L4C381 L Q Q ïC 16-bit Cascadable ALU DEVICES INCORPORATED FEATURES DESCRIPTION □ High-Speed 15ns , Low Power 16-bit Cascadable ALU □ Implements A dd, Subtract, Accu­ mulate, Two's Complement, Pass, and Logic Operations □ All Registers Have a Bypass Path

smd diode f4 4d

Abstract: osa 18 L4C381
Contextual Info: L4C381 L4C381 DEVICES INCORPORATED 16-bit Cascadable ALU 16-bit Cascadable ALU DEVICES INCORPORATED FEATURES DESCRIPTION ❑ High-Speed 15ns , Low Power 16-bit Cascadable ALU ❑ Implements Add, Subtract, Accumulate, Two’s Complement, Pass, and Logic Operations

L4C381

Abstract: P15C
Contextual Info: L4C381 L4C381 DEVICES INCORPORATED 16-bit Cascadable ALU 16-bit Cascadable ALU DEVICES INCORPORATED FEATURES DESCRIPTION ❑ High-Speed 15ns , Low Power 16-bit Cascadable ALU ❑ Implements Add, Subtract, Accumulate, Two’s Complement, Pass, and Logic Operations

CD4089BMS

Abstract: IOH15
Contextual Info: CD4089BMS CMOS Binary Rate Multiplier December 1992 Features conjunction with an up/down counter and control logic used to perform arithmetic operations adds, subtract, divide, raise to a power , solve algebraic and differential equations, generate natural logarithms and trigometric functions, A/D

Contextual Info: ZIS6UIV A m 9512 Arithmetic Processor DISTINCTIVE CHARACTERISTICS • • • • • • • Single 32-bit and double (64-bit) precision capability Add, subtract, multiply and divide functions Compatible with proposed IEEE format Easy interfacing to microprocessors

L4C381EC-40

Contextual Info: L4C381 16-bit Cascadable ALU FEATURES □ High-Speed 15ns , Low Power 16-bit Cascadable ALU □ Implements Add, Subtract, Accu­ mulate, Two's Complement, Pass, and Logic Operations □ All Registers Have a Bypass Path for Complete Flexibility □ DESC SMD No. 5962-89959

Contextual Info: CD4089BMS Semiconductor CMOS Binary Rate Multiplier December 1992 Features conjunction with an up/down counter and control logic used to perform arithmetic operations adds, subtract, divide, raise to a power , solve algebraic and differential equations, generate natural logarithms and trigom etric functions, A/D

CD4089BMS

Abstract: IOH15
Contextual Info: CD4089BMS CMOS Binary Rate Multiplier December 1992 Features conjunction with an up/down counter and control logic used to perform arithmetic operations adds, subtract, divide, raise to a power , solve algebraic and differential equations, generate natural logarithms and trigometric functions, A/D

Contextual Info: IMS A121 2-D Discrete Cosine Transform Image Processor □ratios FEATURES 8 x 8 Transform size. 8 x 8 DCT calculation time = 3.2ps. DC to 20 MHz pixel rate. 9 bit add/subtract input. 12 bit input/output. 14 bit fixed coefficients. Multifunction capability DCT, IDCT, Filter .

Contextual Info: LOGIC DEVICES INC 2bE D • SSbSTQS GQG1353 T ■ L4C381 16-bit Cascadable ALU FEATURES □ High Speed 26 ns , Low Power 16-bit Cascadable ALU □ Implements Add, Subtract, Accu­ mulate, Two's Complement, Pass, and Logic Operations Q All Registers Have a Bypass Path

an1671

Abstract: 300276 LM4562 audio spectrum analyzer led display AN1485 AN-1485 LME49710 LME49720 LME49740 lme49
Contextual Info: National Semiconductor Application Note 1671 Robert A. Pease May 21, 2008 Introduction verter or for a follower. In concept, one could subtract the input from the output, and these deviations could be plotted as a function of VOUT. However, it is nearly impossible to do this

AM9511

Abstract: am9511a4dc am9511a-4dc am9511a Algorithm Details for the Am9511A APU
Contextual Info: V U 9 6 U IV Am 9511A Arithmetic Processor DISTINCTIVE CHARACTERISTICS • • • • 2, 3 and 4MHz operation; fixed point 16-bit and 32-bit operations Floating point 32-bit operations; binary data formats Add, Subtract, Multiply and Divide; trigonometric and

MC14561

Abstract: EAC10 MC14560C I4561 I4560
Contextual Info: MOTOROLA MC14560B NBCO ADDER The MC14560B adds two 4-bit numbers in NBCO natural binary coded decimal format, resulting in sum and carry outputs in NBCD code. This device can also subtract when one set o f inputs is comple­ mented w ith a 9's Complementer (MC14561B).

intel 8231

Abstract: 8098 instruction MCS-85 8231A MCS-80 XX10 8237 DMA Controller
Contextual Info: in te i 8231A ARITHMETIC PROCESSING UNIT Compatible with MCS-80 and MCS-85™ Microprocessor Families Fixed Point Single and Double Precision 16/32 Bit Floating Point Single Precision (32 Bit) Binary Data Formats Add, Subtract, Multiply and Divide Trigonometric and Inverse

wbl47

Abstract: 31A16 SMD L5
Contextual Info: L O G IC L4C 381 16-bit Cascadable ALU DEVICES INCORPORATED FEATURES DESCRIPTION □ High-Speed 15ns , Low Power 16-bit Cascadable ALU □ Implements Add, Subtract, Accu­ mulate, Two's Complement, Pass, and Logic Operations □ All Registers Have a Bypass Path

Contextual Info: L4C381 16-bit Cascadable ALU FEATURES □ High-Speed 15ns , Low Power 16-bit Cascadable ALU □ Implements Add, Subtract, Accu­ mulate, Two’s Complement, Pass, and Logic Operations □ All Registers Have a Bypass Path for Complete Flexibility □ DESC SMD No. 5962-89959

71071

Contextual Info: CD4089BMS fü HARRIS W S E M I C O N D U C T O R CMOS Binary Rate Multiplier Decem ber 1992 Features conjunction with an up/down counter and control logic used to perform arithm etic operations adds, subtract, divide, raise to a power , solve algebraic and differential equations,

TDC1009

Abstract: 2m213 b0538 LMA1009 ma 8630 AO39 200945 b0342
Contextual Info: 1 2 x 1 2-bit Multiplier-Accumulator Features Description □ 45 ns worst-case m ultiplyaccum ulate time □ Low-power CMOS technology □ Replaces TRW TDC1009 □ T w o's com plem ent unsigned, or m ixed operands □ A ccum ulator perform s load, accum ulate, subtract

AM9511

Abstract: am9511a d1783 AM9511A-1
Contextual Info: Am9511A Arithmetic Processor M ILITARY IN FO R M A TIO N VU96UJV DISTINCTIVE CHARACTERISTICS • • • • 2 and 3 MHz operation; fixed point 16-bit and 32-bit operations Floating point 32-bit operations; binary data formats Add, Subtract, Multiply and Divide; trigonometric and

Contextual Info: LMA1008 8 x 8-bit M u ltip lie r-A c c u m u la to r FEATURES □ 20 ns Multiply-Accumulate Time □ Low Power CMOS Technology □ Replaces Raytheon TMC2208 □ Two's Complement or Unsigned Operands □ Accumulator Performs Preload, Accumulate, and Subtract

MC14561

Abstract: mc14070 Two digit bcd adder circuit MC14572 MC14560 MC14530 motorola "mcmos handbook" MC14560B ttl subtracter MC14561B
Contextual Info: MOTOROLA MC14559B See Page 398 SEMICONDUCTOR TECHNICAL DATA MC14560B NBCD Adder L SUFFIX CERAMIC CASE 620 The MC14560B adds two 4–bit numbers in NBCD natural binary coded decimal format, resulting in sum and carry outputs in NBCD code. This device can also subtract when one set of inputs is complemented with