SUM25 Search Results

Contextual Info: SUM25P10-138 Vishay Siliconix P-Channel 100 V D-S MOSFET FEATURES PRODUCT SUMMARY RDS(on) () Max. ID (A)c 0.138 at VGS = - 10 V - 16.3 VDS (V) - 100 0.141 at VGS = - 7.5 V - 16.1 0.142 at VGS = - 6 V - 16.1 Qg (Typ.) 24 nC • TrenchFET Power MOSFET

Contextual Info: SPICE Device Model SUM25P10-138 www.vishay.com Vishay Siliconix P-Channel 100 V D-S MOSFET DESCRIPTION CHARACTERISTICS The attached SPICE model describes the typical electrical characteristics of the p-channel vertical DMOS. The sub-circuit model is extracted and optimized over the -55 °C

RC0038

Abstract: Fast Recovery RC0038D
Contextual Info: SUM20F & FSMS thru SUM50F & FSMS Solid State Devices, Inc. 14701 Firestone Blvd * La Mirada, Ca 90638 Phone: 562 404-7855 * Fax: (562) 404-1773 ssdi@ssdi-power.com * www.ssdi-power.com Designer’s Data Sheet 0.5 AMP 2000-5000 VOLTS 180 nsec HIGH VOLTAGE

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

Contextual Info: LF43891 9 x 9-b it D igital Filter FEATURES_ □ 30 M H z M axim um Sam pling Rate □ 240 M H z M ultiply-Accumulate Rate □ 8 Filter Cells □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Data □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Coefficients

SUM20F

Abstract: SUM25F SUM30F SUM35F SUM40F SUM50F
Contextual Info: SUM20F & FSMS thru SUM50F & FSMS PRELIMINARY SOLID STATE DEVICES, INC. 14830 Valley View Blvd * La Mirada, Ca 90638 Phone: 562 404-7855 * Fax: (562) 404-1773 0.5 AMPS 2000 - 5000 VOLTS 180 nsec HIGH VOLTAGE RECTIFIER 1.30 Designer's Data Sheet FEATURES:

Contextual Info: LF43891 9 x 9-bit Digital Filter D E V IC E S IN C O R P O R A T E D □ □ □ □ 40 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or 9-bit Two's Complement Data/Coefficients □ 26-bit Data Outputs □ Shift-and-Add Output Stage for

Contextual Info: SUM20UF & UFSMS thru SUM50UF & UFSMS Solid State Devices, Inc. 14701 Firestone Blvd * La Mirada, CA 90638 Phone: 562 404-4474 * Fax: (562) 404-1773 ssdi@ssdi-power.com * www.ssdi-power.com Designer’s Data Sheet 0.4 AMP 2000-5000 VOLTS 60 nsec HIGH VOLTAGE

Contextual Info: HSP43168/883 Data Sheet May 1999 Dual FIR Filter Features The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR

Contextual Info: HSP43881/883 Data Sheet May 1999 File Num ber 2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implem ent vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded

Contextual Info: HSP43891/883 ¡33 Digital Filter Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • 0MHz to 25.6MHz Sample Rate • Eight Filter Cells • 9-Bit Coefficients and Signal Data

F10-C2

Abstract: SUM22
Contextual Info: HSP43881/883 TM Data Sheet May 1999 FN2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single

Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.7, September 2012 LatticeECP/EC Family Handbook Table of Contents September 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

SHB15FSMS

Abstract: SHB40FSMS SUM20F SUM25F SUM30F SUM35F SUM40F SUM50F
Contextual Info: SUM20F & FSMS thru SUM50F & FSMS Solid State Devices, Inc. 14701 Firestone Blvd * La Mirada, Ca 90638 Phone: 562 404-7855 * Fax: (562) 404-1773 ssdi@ssdi-power.com * www.ssdi-power.com Designer’s Data Sheet 0.5 AMP 2000-5000 VOLTS 180 nsec HIGH VOLTAGE

Contextual Info: LE43R91 zi;»-«- mm LF43891 9 x 9-bit Digital Filter DEVICES INCORPORATED FEATURES □ □ □ □ DESCRIPTION 40 MHz Maximum Sampling Rate 320 MHz Multiply-AccumulateRate 8 Filter Cells 8-bit Unsigned or 9-bit Two's Complement Data □ 8-bit Unsigned or 9-bit Two's

Contextual Info: LF43891 9 x 9-bit Digital Filter D E V IC E S IN C O R P O R A T E D FEATURES □ 30 M H z M axim um Sam pling Rate □ 320 M H z M ultiply-Accum ulate Rate □ 8 Filter Cells □ 8-bit U nsigned or 9-bit Tw o's Com plem ent Data/Coefficients □ 26-bit Data O utputs

HSP43168

Abstract: circuit diagram for FIR filter B910
Contextual Info: HSP43168/883 TM Data Sheet May 1999 FN3177.3 Dual FIR Filter Features The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR

multiplier accumulator MAC code verilog

Abstract: multiplier accumulator MAC code VHDL algorithm MULT18X18 ispLEVER project Navigator b312 diode SUM30 SUM32 TN1057 vhdl code for floating point subtractor ieee floating point multiplier verilog
Contextual Info: LatticeECP-DSP sysDSP Usage Guide October 2005 Technical Note TN1057 Introduction This technical note discusses how to access the features of the LatticeECP -DSP sysDSP™ Digital Signal Processing Block described in the LatticeECP/EC Family data sheet. Designs targeting the sysDSP Block offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an example of the

Contextual Info: h * 8 HSP43 481/883 Digital Filter August 1992 Description Features • This C ircuit Is Processed in accordance to M il-S td -8 8 3 C and Is Fully C onform ant Paragraph 1.2.1 U nd er th e Provisions of • 0 to 25 .6 M H z S am ple Rate • Four Filter Cells

ISA CODE VHDL

Abstract: 16x4 ram VERILOG IPUG35
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.3, January 2009 LatticeXP2 Family Handbook Table of Contents January 2009 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

prbs pattern generator using vhdl

Abstract: BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.9, April 2011 LatticeECP2/M Family Handbook Table of Contents April 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

Catalog Toshiba

Abstract: st smd diode marking code G11 laser diode head toshiba semiconductor general catalog
Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.3, March 2010 LatticeECP/EC Family Handbook Table of Contents March 2010 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 02.2, February 2007 LatticeECP2/M Family Handbook Table of Contents February 2007 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1

HSP43891

Abstract: HSP43891GC-20 HSP43891GC-25 HSP43891JC-20 HSP43891JC-25 HSP43891JC-30 HSP43891VC-20 HSP43891VC-25 HSP43891VC-30 DIN08
Contextual Info: HSP43891 TM Data Sheet May 1999 Digital Filter Features The HSP43891 is a video-speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in