SY100 Search Results

Contextual Info: 3V LVTTL-TO-DIFFERENTIAL LVPECL AND DIFFERENTIAL LVPECL-TO-LVTTL TRANSLATOR SY10EPT28L SY100EPT28L FINAL FEATURES • 3.3V ±10% power supply ■ Guaranteed AC parameters over temperature: fMAX > 275MHz LVTTL ■ < 2ns LVPECL-to-LVTTL propagation delay ■ < 600ps LVTTL-to-LVPECL propagation delay

Contextual Info: PECL-TO-CML TRANSLATOR w/o ENABLE FEATURES • ■ ■ ■ ■ ■ ■ ■ SY100ELT982 DESCRIPTION Up to 1.25Gbps operation 25mA peak drive current Adjustable output current Separate output enable Differential inputs for data 75KΩ input pull-down resistor

elt25

Contextual Info: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL translator. Because ECL levels are used, a +5V, –5.2V

Contextual Info: QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ SY100E417 3.3V and 5V power supplies required Also, supports LVPECL-to-PECL translation 500ps propagation delays Fully differential design Differential line receiver capability

z162

Contextual Info: ÷1, ÷2, ÷4 OR (÷2, ÷4, ÷8) CLOCK GENERATION CHIP Micrel, Inc. Precision Edge SY100S834 SY100S834L Edge® SY100S834 SY100S834L FEATURES • ■ ■ ■ ■ ■ 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable

Contextual Info: Precision Edge SY10ELT20V SY100ELT20V FINAL FEATURES • ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply options 300ps typical propagation delay Low power Differential PECL output PNP TTL input for minimal loading Flow-through pinouts Available in 8-pin SOIC package

Contextual Info: 5V/3.3V 2.5Gbps VARIABLE OUTPUT SWING DIFFERENTIAL RECEIVER SY100EP16VS FINAL FEATURES • 3.3V and 5V power supply options ■ Fast output transitions <160ps tr / tf ECL Pro ■ Guaranteed operation over –40°C to +85°C temperature range ■ Functionally equivalent to SY88927V and

Contextual Info: 3.3V 1:4 CLOCK DISTRIBUTION FEATURES • ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power

PS235

Contextual Info: *SYNERGY SY10EL52 SY100EL52 DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP S E M IC O N D U C T O R FEATURES • DESCRIPTION ■ 3 65ps propagation delay The c lo c k ■ 2.0GHz toggle frequency S Y 1 0 /1 0 0 E L 5 2 D flip - f lo p s a re w it h d if fe r e n t ia l d a ta , d if fe r e n t ia l

Contextual Info: * 5 V / 3 . 3 V ^2. + 4 /6 C L O C K SYNERGY Clockworks G E N E R A T I O N C H IP SY100EL38/L SEMICONDUCTOR DESCRIPTION FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable M aster Reset for synchronization Internal 75KQ input pull-down resistors

Contextual Info: * DUAL SUPPLY SYNERGY o c ta l e c l-to -ttl S E M IC O N D U C T O R Clockworks s y io o h a b « SY100HA643 DESCRIPTION FEATURES E C L /T T L v e rs io n o f p o p u la r E C L in P S ™ E 1 11 4 0 0 p s w ith in d e v ic e sk ew 8 0 0 p s p a rt-to -p a rt s k e w

Contextual Info: c* SY10EL01 SY100EL01 4-INPUT OR/NOR SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 230ps propagation delay The SY10/100EL01 are 4-input OR/NOR gates. These devices are functionally equivalent to the E101 devices, with higher performance capabilities. With propagation

Contextual Info: .M i P ln r k W n r k c ^ 3.3V SINGLE SUPPLY 1:9 PECL-TO-TTL SYNERGY PRELIMINARY SY10H641L SY100H641L SEM ICONDUCTOR FEATURES DESCRIPTION • 3 .3 V p o w e r s u p p ly ■ P E C L -to -T T L v e rs io n o f p o p u la r E C L in P S E111 ■ G u a ra n te e d lo w s k e w s p e c ific a tio n

Contextual Info: *SYNERGY SY10EL04 SY100EL04 2-INPUT AND/NAND S E M IC O N D U C T O R FEATURES DESCRIPTION • 240ps propagation delay The S Y 1 0/1 0 0 E L 0 4 are 2 -in p u t A N D /N A N D gates. T hese devices are function a lly eq u iva le nt to the E104 d e vice s, w ith h ig h e r p e rfo rm a n ce c a p a b ilitie s .

ic 192 ttl

Contextual Info: 3.3V SINGLE SUPPLY Q UAD V P E C L T O .T T I S YN ER G Y ° WITH LATCHED O UTPUT ENABLE S M tC O N D U C T O R Clockworks PRELIMINARY SY10H842L SY100H842L DESCRIPTION FEATURES • 3.3V power supply ■ Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew

LD 757 ps

Contextual Info: * LOW POW ER HEX TTL-to-ECL TRANSLATO R SYNERGY SY100S324 S E M IC O N D U C T O R DESCRIPTION FEATURES Max. propagation delay of 1.4ns The SY100S324 is a hex translator designed to convert T T L logic levels to 100K ECL levels. The inputs are TTL com patible with diffe re n tia l o utputs that can e ith e r be

ic 3525 internal block diagram

Abstract: s815
Contextual Info: * SINGLE SUPPLY QUAD SYNERGY C lockworks SY100S815 PECL/TTL-TO-PECL SEMICONDUCTOR FEATURES • ■ Quad PECL version of popular ECLinPS El 11 ■ Low skew ■ Guaranteed skew spec ■ TTL enable Input ■ Selectable TTL or PECL clock input ■ Single +5V supply

Contextual Info: * C lo c k w o rk s SY10EL34/L SY100EL34/L 5V/3.3V +2, +4, ^8 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps ou tput-to-output skew Synchronous enable/disable Master Reset fo r synchronization Internal 75KQ input pull-down resistors

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • 525ps propagation delay The S Y 10 /1 00EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flop when the clock is LO W and is tran sfe rre d to the slave and,

Contextual Info: O SING LE SUPPLY PEC L-TTL 1:4 C LO C K DRIVER SYNERGY S E M IC O N D U C T O R FEATURES S Y ^o'lo'ohS l DESCRIPTION • Translates positive ECL to TTL PECL-TTL The SY10H841 and SY100H841 are single supply, low skew translating 1:4 clock drivers. The devices feature a 24m A TTL output stage, with AC

Contextual Info: SING LE SUPPLY Q U A D P EC L-TO -TTL Clockworks SY10H842 W /LA TC H E D O UTPUT E N A B L E sÈ llb ólÌD U C T O R SY100H842 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

Contextual Info: * 9-BIT LATCHED ECL-TO -TTL SYNERGY SY10H603 SY100H603 S E M IC O N D U C T O R FEATURES DESCRIPTION 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply

100E196

Contextual Info: * C lo c k w o rk s SY10E196 SY100E196 P R O G R A M M A B L E DELAY CHIP WITH A N A L O G INPUT SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • Up to 2ns delay range ■ Extended 100E V ee range of -4.2V to -5.5V ■ ~20ps digital step resolution

F100K

Abstract: SY100S304 SY100S304FC SY100S304JC SY100S304JCTR
Contextual Info: QUINT AND/NAND GATE FEATURES SY100S304 DESCRIPTION • Max. propagation delay of 1050ps ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors