SY100S838LZCTR Search Results

SY100S838LZCTR Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF	PDF Size	Page count
SY100S838LZCTR		Micrel Semiconductor	(Divide 1, Divide 2/3) OR (Divide 2, Divide 4/6) CLOCK GENERATION CHIP		Original	PDF	74.02KB	4

SY100S838LZCTR Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
100S838L Contextual Info: V • SYNERGY 2n s o r ' : a 4 ei : ;.o c k î î e n f r a m ^ Z M c v H a w .„ if \8 S E M IC O N D U C 1O R F EA TU R E S D ES C R IPTIO N • 3.3V and 5V pow er supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ M aster Reset for synchronization	OCR Scan	75Ki2 20-pin SY100S838ZC SY100S838ZCTR SY100S838LZC SY100S838LZCTR Z20-1 Z20-1 100S838L	PDF
113006 Abstract: SY100S838ZC SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZCTR SY100S838ZI SY100S838LZGTR Contextual Info: ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP Micrel, Inc. Precision Edge Precision SY100S838 Edge® SY100S838L SY100S838 SY100S838L FEATURES • ■ ■ ■ ■ ■ 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable	Original	SY100S838 SY100S838L 20-pin SY100S838/L M9999-113006 113006 SY100S838ZC SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZCTR SY100S838ZI SY100S838LZGTR	PDF
SY100S838 Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR 100S838L Contextual Info: SYNERGY ClockWorks SY100S838 ClockWorks™ SY100S838L ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP SEMICONDUCTOR SYNERGY SY100S838 SY100S838L SEMICONDUCTOR FEATURES DESCRIPTION • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable	Original	SY100S838 SY100S838L SY100S838ZC Z20-1 SY100S838ZCTR SY100S838LZC SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR 100S838L	PDF
Contextual Info: +1, +2/3 OR (+2, * 4 /6 ) c l o c k g e n e r a t i o n c h ip SYNERG Y C'QS 0 S 8 3 8 s y io o s s 3 8 l SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization	OCR Scan	0S838 20-pin SY100S838/L	PDF
SY100S838 Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR Contextual Info: ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are	Original	SY100S838/L SY100S838LZI Z20-1 SY100S838LZITR SY100S838 SY100S838L Z20-1) SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR	PDF
SY100S838 Abstract: SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR Contextual Info: ClockWorks SY100S838 SY100S838L FINAL ÷1, ÷2/3 OR (÷2, ÷4/6) CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION The SY100S838/L is a low skew (÷1, ÷2/3) or (÷2, ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are	Original	SY100S838 SY100S838L SY100S838/L 0SY100S838LZI Z20-1 SY100S838LZITR Z20-1) SY100S838 SY100S838L SY100S838LZC SY100S838LZCTR SY100S838ZC SY100S838ZCTR	PDF