T90PII Search Results

Contextual Info: Advance information •■ I l AS4LC2M8S0 AS4LC1M1ÓS0 A 3.3V 2 M x 8 /lM x 16 CMOS synchronous DRAM Features Automatic and direct precharge Burst read, single write Can assert random column address in every cycle LVl'l'L compatible V O 3.3Vpower supply JEDEC standard package, pinout and function

Contextual Info: AS7C4096 AS7C34096 A 5V/3.3V 512Kx8 CMOS SRAM Features • Organization: 262,144 words x 16 bits • High speed - 12/15/ 20/ 25 ns address access time - 5/ 5/ 617 ns output enable access time • Law power consumption - .Active: 990 mW max 20 ns cycle, 5V

Contextual Info: Enhanced IVfemoiy Systems be. DM512K32ST/DM512K36ST 512Kb x 32/512Kb x 36 EDRAM SIMM Product Specification Features A rchitecture • 4KByte SRAM Cache Memory for 12ns Random Reads Within Four s tiv e s Pages Multibank Cache ■ Fast DRAM Array for 30ns Access to Any New Page

Contextual Info: F n h fl n rp H DM2203/2213 Multibank EDOEDRAM 5 1 2 K b * 8 Product Specification H Features • 8Kbit SRAM Cache Memory for 12ns Random Reads Within Four Active Pages Mu iti bank Cache ■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page ■ Write Posting Ftegister for 12ns Random Writes and Burst Writes

Contextual Info: Enhanced DM1M64DTE/DM1M72DTE M ultibank Burst EDOEDRAM 1Mb x 64/1Mb x 72 Enhanced DRAM DIMM IVfemoiy Suterns be. H Product Specification Features row register over a 2Kbyte-wide bus in just 18ns for an effective cache • 16Kbytes SRAM Cache Memory for 12ns Random Reads Within

Contextual Info: Enhanced IVfemoiy Systems Inc. DM512K32ST6/DM512K36ST6 Multibank EDO 512Kb x 32/512Kb x 36 EDRAM SIMM Product Specification Features Architecture • 4KByte SRAM Cache Memory for 12ns Random Reads Within Four stive s Pages Multibank Cache ■ Fast DRAM Array for 30ns Access to Any New Page

U23C-36

Contextual Info: •K p n h o n p p f V i i DM 1M64DT6/DM1M72DT6 Multibank EDOEDRAM m m * d 1 2 ra m d i m m ProductSpecification Features ■ 16Kbytes SAM Cache Memory for 12ns Random Reads Within Eght Active Pages Multi bank CSche ■ Fast 8Mbyte DRAM Array for 30ns Access to Any New Page

Contextual Info: •K Pnha nppH 16MBit Enhanced SDRAM Family M W « 1Mbx16 *7 1 Preliminary Features ■ Pin and Timing Compatible with I ndustry Standard SDRAM ■ Synchronous Clock Operation at Burst Rates Up to 166 MHz ■ Fast 30ns 16Mbit DRAM Organized in 2 Banks of 8Mbits

UAA 1006

Abstract: AS4LC1M16SO AS4LC1M16S0 1024x512x8 DTA 1006
Contextual Info: Advance informatio AS4LC 2M8S0 AS4LC1 M16S0 3.3V 2 M x 8 /lM x 1 6 CMOS synchronous DRAM Features A utom atic and direct precharge B urst read, single w rite Can assert ra n d o m co lu m n address in every cycle LVTTL co m patible V O 3 .3 Y p o w e r supply

Contextual Info: Enhanced DM2223/2233 Multibank Burst EDOEDRAM 512Kb x 8 Enhanced Dynamic RAM I V f e m o iy S y s t e m s In c . Product Specification Features • 8Kbit SRAM Cache Memory for 12ns Random Reads Within Four Active Pages Multi bank Cache ■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page

Contextual Info: Advance information •■ I l AS4LC2M8S0 AS4LC1M1ÓS0 A 3.3V 2 M x 8 /lM x 16 CMOS synchronous DRAM Features Automatic and direct precharge Burst read, single write Can assert random column address in every cycle LVl'l'L compatible V O 3.3Vpower supply JEDEC standard package, pinout and function

Contextual Info: AS7C1026 AS7C31026 A 5V/3.3V 64Kx 16 CMOS SRAM Features • Organization: 262,144 words x 16 bits • High speed - 1 2 /1 5 / 20/ 25 ns address access time - 5/ 5/ 6 1 7 ns output enable access time • Law power consumption - .Active: 770 mW max 20 ns cycle, 5V

Contextual Info: Enhanced IVfemoiySuterns be. DM512K64DT6/DM512K72DT6 Multibank EDO EDRAM 512Kb x 64/512Kb x 12 Enhanced DRAM DIMM Product Specification Features • 8 Kbytes SRAM Cache Memory for 12ns Random Reads Within Four Active Pages Multi bank Cache ■ Fast 4Mbyte DRAM Array for 30ns Access to Any New Page